[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PATCH v2 14/17] target/riscv: Only support little endian guests
From: |
Alistair Francis |
Subject: |
[PATCH v2 14/17] target/riscv: Only support little endian guests |
Date: |
Thu, 4 Jun 2020 18:21:21 -0700 |
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/csr.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 973404d0aa..5b64539efb 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -772,6 +772,8 @@ static int read_hstatus(CPURISCVState *env, int csrno,
target_ulong *val)
/* We only support 64-bit VSXL */
*val = set_field(*val, HSTATUS_VSXL, 2);
#endif
+ /* We only support little endian */
+ *val = set_field(*val, HSTATUS_VSBE, 0);
return 0;
}
@@ -783,6 +785,9 @@ static int write_hstatus(CPURISCVState *env, int csrno,
target_ulong val)
qemu_log_mask(LOG_UNIMP, "QEMU does not support mixed HSXLEN
options.");
}
#endif
+ if (get_field(val, HSTATUS_VSBE) != 0) {
+ qemu_log_mask(LOG_UNIMP, "QEMU does not support big endian guests.");
+ }
return 0;
}
--
2.26.2
- Re: [PATCH v2 04/17] target/riscv: Implement checks for hfence, (continued)
- [PATCH v2 05/17] target/riscv: Allow setting a two-stage lookup in the virt status, Alistair Francis, 2020/06/04
- [PATCH v2 11/17] target/riscv: Update the Hypervisor trap return/entry, Alistair Francis, 2020/06/04
- [PATCH v2 12/17] target/riscv: Update the CSRs to the v0.6 Hyp extension, Alistair Francis, 2020/06/04
- [PATCH v2 07/17] target/riscv: Do two-stage lookups on hlv/hlvx/hsv instructions, Alistair Francis, 2020/06/04
- [PATCH v2 06/17] target/riscv: Allow generating hlv/hlvx/hsv instructions, Alistair Francis, 2020/06/04
- [PATCH v2 08/17] target/riscv: Don't allow guest to write to htinst, Alistair Francis, 2020/06/04
- [PATCH v2 09/17] target/riscv: Convert MSTATUS MTL to GVA, Alistair Francis, 2020/06/04
- [PATCH v2 13/17] target/riscv: Only support a single VSXL length, Alistair Francis, 2020/06/04
- [PATCH v2 10/17] target/riscv: Fix the interrupt cause code, Alistair Francis, 2020/06/04
- [PATCH v2 14/17] target/riscv: Only support little endian guests,
Alistair Francis <=
- [PATCH v2 15/17] target/riscv: Support the v0.6 Hypervisor extension CRSs, Alistair Francis, 2020/06/04
- [PATCH v2 16/17] target/riscv: Return the exception from invalid CSR accesses, Alistair Francis, 2020/06/04
- [PATCH v2 17/17] target/riscv: Support the Virtual Instruction fault, Alistair Francis, 2020/06/04