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From: | Jim Wilson |
Subject: | Re: [PATCH v2] target/riscv: Expose "priv" register for GDB |
Date: | Mon, 7 Oct 2019 14:16:56 -0700 |
User-agent: | Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.8.0 |
On 10/4/19 8:16 AM, Jonathan Behrens wrote:
diff --git a/gdb-xml/riscv-32bit-cpu.xml b/gdb-xml/riscv-32bit-cpu.xml index 0d07aaec85..d6d76aafd8 100644 --- a/gdb-xml/riscv-32bit-cpu.xml +++ b/gdb-xml/riscv-32bit-cpu.xml @@ -44,4 +44,5 @@ <reg name="t5" bitsize="32" type="int"/> <reg name="t6" bitsize="32" type="int"/> <reg name="pc" bitsize="32" type="code_ptr"/> + <reg name="priv" bitsize="32" type="int"/> </feature>
Adding this to the cpu register set means that the gdb "info registers" command will now list a value for the mysterious undocumented "priv" register. That is likely to result in user confusion, and a few gdb bug reports.
Gdb incidentally already has support for a virtual priv register. From gdb/riscv-tdep.c:
static const struct riscv_register_feature riscv_virtual_feature = { "org.gnu.gdb.riscv.virtual", { { RISCV_PRIV_REGNUM, { "priv" }, false } } };So the correct way to fix this is to add a gdb-xml/riscv-32bit-virtual.xml file, along with code to handle this new xml file and the registers in it. Likewise for the 64-bit support.
The main advantage of doing things this way is that only people that care about the priv register will see it, and this will interoperate with other RISC-V debuggers and targets (if any) that already have virtual priv register support.
Jim
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