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[Qemu-riscv] [PULL 36/48] riscv: sifive_u: Reference PRCI clocks in UART
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 36/48] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes |
Date: |
Wed, 18 Sep 2019 07:56:28 -0700 |
From: Bin Meng <address@hidden>
Now that we have added a PRCI node, update existing UART and ethernet
nodes to reference PRCI as their clock sources, to keep in sync with
the Linux kernel device tree.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 7 ++++---
include/hw/riscv/sifive_u_prci.h | 10 ++++++++++
2 files changed, 14 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index f6b868f49b..9e698a11c4 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -78,7 +78,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
int cpu;
uint32_t *cells;
char *nodename;
- char ethclk_names[] = "pclk\0hclk\0tx_clk";
+ char ethclk_names[] = "pclk\0hclk";
uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
uint32_t uartclk_phandle;
uint32_t hfclk_phandle, rtcclk_phandle;
@@ -263,7 +263,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ);
qemu_fdt_setprop_cells(fdt, nodename, "clocks",
- ethclk_phandle, ethclk_phandle, ethclk_phandle);
+ prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL);
qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names,
sizeof(ethclk_names));
qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1);
@@ -293,7 +293,8 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cells(fdt, nodename, "reg",
0x0, memmap[SIFIVE_U_UART0].base,
0x0, memmap[SIFIVE_U_UART0].size);
- qemu_fdt_setprop_cell(fdt, nodename, "clocks", uartclk_phandle);
+ qemu_fdt_setprop_cells(fdt, nodename, "clocks",
+ prci_phandle, PRCI_CLK_TLCLK);
qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);
qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ);
diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h
index 60a2eab0e9..0a531fdadc 100644
--- a/include/hw/riscv/sifive_u_prci.h
+++ b/include/hw/riscv/sifive_u_prci.h
@@ -78,4 +78,14 @@ typedef struct SiFiveUPRCIState {
uint32_t clkmuxstatus;
} SiFiveUPRCIState;
+/*
+ * Clock indexes for use by Device Tree data and the PRCI driver.
+ *
+ * These values are from sifive-fu540-prci.h in the Linux kernel.
+ */
+#define PRCI_CLK_COREPLL 0
+#define PRCI_CLK_DDRPLL 1
+#define PRCI_CLK_GEMGXLPLL 2
+#define PRCI_CLK_TLCLK 3
+
#endif /* HW_SIFIVE_U_PRCI_H */
--
2.21.0
- [Qemu-riscv] [PULL 23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, (continued)
- [Qemu-riscv] [PULL 23/48] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 25/48] riscv: sifive_e: prci: Update the PRCI register block size, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 26/48] riscv: sifive_e: Drop sifive_mmio_emulate(), Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 29/48] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 27/48] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 32/48] riscv: sifive_u: Update PLIC hart topology configuration string, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 28/48] riscv: hart: Extract hart realize to a separate routine, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 30/48] riscv: sifive_u: Set the minimum number of cpus to 2, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 31/48] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 33/48] riscv: sifive: Implement PRCI model for FU540, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 36/48] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 34/48] riscv: sifive_u: Generate hfclk and rtcclk nodes, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 37/48] riscv: sifive_u: Update UART base addresses and IRQs, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 38/48] riscv: sifive_u: Change UART node name in device tree, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 35/48] riscv: sifive_u: Add PRCI block to the SoC, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 41/48] riscv: sifive_u: Instantiate OTP memory with a serial number, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 40/48] riscv: sifive: Implement a model for SiFive FU540 OTP, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 43/48] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 39/48] riscv: roms: Update default bios for sifive_u machine, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 45/48] target/riscv: Use both register name and ABI name, Palmer Dabbelt, 2019/09/18
- [Qemu-riscv] [PULL 42/48] riscv: sifive_u: Fix broken GEM support, Palmer Dabbelt, 2019/09/18