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[Qemu-riscv] [PULL 43/47] riscv: sifive_u: Remove handcrafted clock node
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 43/47] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet |
Date: |
Tue, 10 Sep 2019 12:05:09 -0700 |
From: Bin Meng <address@hidden>
In the past we did not have a model for PRCI, hence two handcrafted
clock nodes ("/soc/ethclk" and "/soc/uartclk") were created for the
purpose of supplying hard-coded clock frequencies. But now since we
have added the PRCI support in QEMU, we don't need them any more.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/sifive_u.c | 24 +-----------------------
include/hw/riscv/sifive_u.h | 3 +--
2 files changed, 2 insertions(+), 25 deletions(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 3b61fab42c..507a6e2fa9 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -87,8 +87,7 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
uint32_t *cells;
char *nodename;
char ethclk_names[] = "pclk\0hclk";
- uint32_t plic_phandle, prci_phandle, ethclk_phandle, phandle = 1;
- uint32_t uartclk_phandle;
+ uint32_t plic_phandle, prci_phandle, phandle = 1;
uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle;
fdt = s->fdt = create_device_tree(&s->fdt_size);
@@ -248,17 +247,6 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
g_free(cells);
g_free(nodename);
- ethclk_phandle = phandle++;
- nodename = g_strdup_printf("/soc/ethclk");
- qemu_fdt_add_subnode(fdt, nodename);
- qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
- qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
- qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency",
- SIFIVE_U_GEM_CLOCK_FREQ);
- qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle);
- ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
- g_free(nodename);
-
phy_phandle = phandle++;
nodename = g_strdup_printf("/soc/ethernet@%lx",
(long)memmap[SIFIVE_U_GEM].base);
@@ -292,16 +280,6 @@ static void create_fdt(SiFiveUState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
g_free(nodename);
- uartclk_phandle = phandle++;
- nodename = g_strdup_printf("/soc/uartclk");
- qemu_fdt_add_subnode(fdt, nodename);
- qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock");
- qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0);
- qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400);
- qemu_fdt_setprop_cell(fdt, nodename, "phandle", uartclk_phandle);
- uartclk_phandle = qemu_fdt_get_phandle(fdt, nodename);
- g_free(nodename);
-
nodename = g_strdup_printf("/soc/serial@%lx",
(long)memmap[SIFIVE_U_UART0].base);
qemu_fdt_add_subnode(fdt, nodename);
diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h
index 5270851aa2..e4df298c23 100644
--- a/include/hw/riscv/sifive_u.h
+++ b/include/hw/riscv/sifive_u.h
@@ -77,8 +77,7 @@ enum {
enum {
SIFIVE_U_CLOCK_FREQ = 1000000000,
SIFIVE_U_HFCLK_FREQ = 33333333,
- SIFIVE_U_RTCCLK_FREQ = 1000000,
- SIFIVE_U_GEM_CLOCK_FREQ = 125000000
+ SIFIVE_U_RTCCLK_FREQ = 1000000
};
#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1
--
2.21.0
- [Qemu-riscv] [PULL 33/47] riscv: sifive: Implement PRCI model for FU540, (continued)
- [Qemu-riscv] [PULL 33/47] riscv: sifive: Implement PRCI model for FU540, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 35/47] riscv: sifive_u: Add PRCI block to the SoC, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 36/47] riscv: sifive_u: Reference PRCI clocks in UART and ethernet nodes, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 34/47] riscv: sifive_u: Generate hfclk and rtcclk nodes, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 37/47] riscv: sifive_u: Update UART base addresses and IRQs, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 38/47] riscv: sifive_u: Change UART node name in device tree, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 40/47] riscv: sifive: Implement a model for SiFive FU540 OTP, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 41/47] riscv: sifive_u: Instantiate OTP memory with a serial number, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 42/47] riscv: sifive_u: Fix broken GEM support, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 44/47] riscv: sifive_u: Update model and compatible strings in device tree, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 43/47] riscv: sifive_u: Remove handcrafted clock nodes for UART and ethernet,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 39/47] riscv: roms: Update default bios for sifive_u machine, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 45/47] target/riscv: Use both register name and ABI name, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 47/47] target/riscv: Use TB_FLAGS_MSTATUS_FS for floating point, Palmer Dabbelt, 2019/09/11
- [Qemu-riscv] [PULL 46/47] target/riscv: Fix mstatus dirty mask, Palmer Dabbelt, 2019/09/11
- Re: [Qemu-riscv] [PULL] RISC-V Patches for the 4.2 Soft Freeze, Part 1, Peter Maydell, 2019/09/13