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[Qemu-riscv] [PATCH v8 07/32] riscv: hw: Change to use qemu_log_mask(LOG
From: |
Bin Meng |
Subject: |
[Qemu-riscv] [PATCH v8 07/32] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead |
Date: |
Fri, 6 Sep 2019 09:19:54 -0700 |
Replace the call to hw_error() with qemu_log_mask(LOG_GUEST_ERROR,...)
in various sifive models.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v8: None
Changes in v7: None
Changes in v6: None
Changes in v5:
- new patch to change to use qemu_log_mask(LOG_GUEST_ERROR,...) instead
in various sifive models
Changes in v4: None
Changes in v3: None
Changes in v2: None
hw/riscv/sifive_prci.c | 8 +++++---
hw/riscv/sifive_test.c | 5 +++--
hw/riscv/sifive_uart.c | 9 +++++----
3 files changed, 13 insertions(+), 9 deletions(-)
diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c
index 562bc3d..982fbb2 100644
--- a/hw/riscv/sifive_prci.c
+++ b/hw/riscv/sifive_prci.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "hw/sysbus.h"
+#include "qemu/log.h"
#include "qemu/module.h"
#include "target/riscv/cpu.h"
#include "hw/hw.h"
@@ -38,7 +39,8 @@ static uint64_t sifive_prci_read(void *opaque, hwaddr addr,
unsigned int size)
case SIFIVE_PRCI_PLLOUTDIV:
return s->plloutdiv;
}
- hw_error("%s: read: addr=0x%x\n", __func__, (int)addr);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n",
+ __func__, (int)addr);
return 0;
}
@@ -66,8 +68,8 @@ static void sifive_prci_write(void *opaque, hwaddr addr,
s->plloutdiv = (uint32_t) val64;
break;
default:
- hw_error("%s: bad write: addr=0x%x v=0x%x\n",
- __func__, (int)addr, (int)val64);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
+ __func__, (int)addr, (int)val64);
}
}
diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index 7117409..aa544e7 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -20,6 +20,7 @@
#include "qemu/osdep.h"
#include "hw/sysbus.h"
+#include "qemu/log.h"
#include "qemu/module.h"
#include "sysemu/runstate.h"
#include "target/riscv/cpu.h"
@@ -49,8 +50,8 @@ static void sifive_test_write(void *opaque, hwaddr addr,
break;
}
}
- hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n",
- __func__, (int)addr, val64);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64
"\n",
+ __func__, (int)addr, val64);
}
static const MemoryRegionOps sifive_test_ops = {
diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c
index 9de42b1..215990b 100644
--- a/hw/riscv/sifive_uart.c
+++ b/hw/riscv/sifive_uart.c
@@ -18,6 +18,7 @@
#include "qemu/osdep.h"
#include "qapi/error.h"
+#include "qemu/log.h"
#include "hw/sysbus.h"
#include "chardev/char.h"
#include "chardev/char-fe.h"
@@ -95,8 +96,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size)
return s->div;
}
- hw_error("%s: bad read: addr=0x%x\n",
- __func__, (int)addr);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n",
+ __func__, (int)addr);
return 0;
}
@@ -127,8 +128,8 @@ uart_write(void *opaque, hwaddr addr,
s->div = val64;
return;
}
- hw_error("%s: bad write: addr=0x%x v=0x%x\n",
- __func__, (int)addr, (int)value);
+ qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n",
+ __func__, (int)addr, (int)value);
}
static const MemoryRegionOps uart_ops = {
--
2.7.4
- [Qemu-riscv] [PATCH v8 00/32] riscv: sifive_u: Improve the emulation fidelity of sifive_u machine, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 01/32] riscv: hw: Remove duplicated "hw/hw.h" inclusion, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 02/32] riscv: sifive_test: Add reset functionality, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 05/32] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 03/32] riscv: hw: Remove superfluous "linux, phandle" property, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 04/32] riscv: hw: Use qemu_fdt_setprop_cell() for property with only 1 cell, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 08/32] riscv: hw: Remove the unnecessary include of target/riscv/cpu.h, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 12/32] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 07/32] riscv: hw: Change to use qemu_log_mask(LOG_GUEST_ERROR, ...) instead,
Bin Meng <=
- [Qemu-riscv] [PATCH v8 09/32] riscv: roms: Remove executable attribute of opensbi images, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 06/32] riscv: hw: Change create_fdt() to return void, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 13/32] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 10/32] riscv: sifive_u: Remove the unnecessary include of prci header, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 16/32] riscv: hart: Extract hart realize to a separate routine, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 14/32] riscv: sifive_e: Drop sifive_mmio_emulate(), Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 15/32] riscv: Add a sifive_cpu.h to include both E and U cpu type defines, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 11/32] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/09/06
- [Qemu-riscv] [PATCH v8 17/32] riscv: hart: Add a "hartid-base" property to RISC-V hart array, Bin Meng, 2019/09/06