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[Qemu-riscv] [PATCH v2 10/28] riscv: sifive_u: Remove the unnecessary in
From: |
Bin Meng |
Subject: |
[Qemu-riscv] [PATCH v2 10/28] riscv: sifive_u: Remove the unnecessary include of prci header |
Date: |
Wed, 7 Aug 2019 00:45:06 -0700 |
sifive_u machine does not use PRCI as of today. Remove the prci
header inclusion.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
---
Changes in v2: None
hw/riscv/sifive_u.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index ea45e77..7557026 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -41,7 +41,6 @@
#include "hw/riscv/sifive_plic.h"
#include "hw/riscv/sifive_clint.h"
#include "hw/riscv/sifive_uart.h"
-#include "hw/riscv/sifive_prci.h"
#include "hw/riscv/sifive_u.h"
#include "hw/riscv/boot.h"
#include "chardev/char.h"
--
2.7.4
- [Qemu-riscv] [PATCH v2 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, (continued)
- [Qemu-riscv] [PATCH v2 12/28] riscv: sifive_e: prci: Fix a typo of hfxosccfg register programming, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 08/28] riscv: sifive_u: Update PLIC hart topology configuration string, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 15/28] riscv: sifive_u: Generate hfclk and rtcclk nodes, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Bin Meng, 2019/08/07
- Re: [Qemu-riscv] [Qemu-devel] [PATCH v2 11/28] riscv: sifive: Rename sifive_prci.{c, h} to sifive_e_prci.{c, h}, Alistair Francis, 2019/08/09
- [Qemu-riscv] [PATCH v2 10/28] riscv: sifive_u: Remove the unnecessary include of prci header,
Bin Meng <=
- [Qemu-riscv] [PATCH v2 06/28] riscv: sifive_u: Update hart configuration to reflect the real FU540 SoC, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 19/28] riscv: sifive_u: Instantiate OTP memory with a serial number, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 05/28] riscv: hart: Support heterogeneous harts population, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 13/28] riscv: sifive_e: prci: Update the PRCI register block size, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 22/28] riscv: sifive_u: Generate an aliases node in the device tree, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 17/28] riscv: sifive_u: Change UART node name in device tree, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 16/28] riscv: sifive_u: Add PRCI block to the SoC, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 14/28] riscv: sifive: Implement PRCI model for FU540, Bin Meng, 2019/08/07
- [Qemu-riscv] [PATCH v2 25/28] riscv: hw: Remove not needed PLIC properties in device tree, Bin Meng, 2019/08/07