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[Qemu-riscv] [PULL 11/32] riscv: virt: Correct pci "bus-range" encoding
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 11/32] riscv: virt: Correct pci "bus-range" encoding |
Date: |
Wed, 3 Jul 2019 01:40:27 -0700 |
From: Bin Meng <address@hidden>
The largest pci bus number should be calculated from ECAM size,
instead of its base address.
Signed-off-by: Bin Meng <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 84d94d0c42d8..487f61404b21 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -298,7 +298,7 @@ static void *create_fdt(RISCVVirtState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci");
qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0);
qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0,
- memmap[VIRT_PCIE_ECAM].base /
+ memmap[VIRT_PCIE_ECAM].size /
PCIE_MMCFG_SIZE_MIN - 1);
qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0);
qemu_fdt_setprop_cells(fdt, nodename, "reg", 0,
memmap[VIRT_PCIE_ECAM].base,
--
2.21.0
- [Qemu-riscv] [PULL 01/32] target/riscv: Allow setting ISA extensions via CPU props, (continued)
- [Qemu-riscv] [PULL 01/32] target/riscv: Allow setting ISA extensions via CPU props, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 03/32] target/riscv: Fix PMP range boundary address bug, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 02/32] sifive_prci: Read and write PRCI registers, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 05/32] RISC-V: Only Check PMP if MMU translation succeeds, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 04/32] target/riscv: Implement riscv_cpu_unassigned_access, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 06/32] RISC-V: Raise access fault exceptions on PMP violations, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 07/32] RISC-V: Check for the effective memory privilege mode during PMP checks, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 08/32] RISC-V: Check PMP during Page Table Walks, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 09/32] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 10/32] RISC-V: Fix a PMP check with the correct access size, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 11/32] riscv: virt: Correct pci "bus-range" encoding,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 12/32] RISC-V: Fix a memory leak when realizing a sifive_e, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 13/32] target/riscv: Restructure deprecatd CPUs, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 14/32] target/riscv: Add the privledge spec version 1.11.0, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 17/32] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 15/32] target/riscv: Add the mcountinhibit CSR, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 16/32] target/riscv: Set privledge spec 1.11.0 as default, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 18/32] target/riscv: Require either I or E base extension, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 20/32] target/riscv: Add support for disabling/enabling Counters, Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 24/32] RISC-V: Update syscall list for 32-bit support., Palmer Dabbelt, 2019/07/03
- [Qemu-riscv] [PULL 19/32] target/riscv: Remove user version information, Palmer Dabbelt, 2019/07/03