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[Qemu-riscv] [PULL 25/34] riscv: virt: Add cpu-topology DT node.
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 25/34] riscv: virt: Add cpu-topology DT node. |
Date: |
Fri, 28 Jun 2019 10:32:18 -0700 |
From: Atish Patra <address@hidden>
Currently, there is no cpu topology defined in RISC-V.
Define a device tree node that clearly describes the
entire topology. This saves the trouble of scanning individual
cache to figure out the topology.
Here is the linux kernel patch series that enables topology
for RISC-V.
http://lists.infradead.org/pipermail/linux-riscv/2019-June/005072.html
CPU topology after applying this patch in QEMU & above series in kernel
/ # cat /sys/devices/system/cpu/cpu2/topology/thread_siblings_list
2
/ # cat /sys/devices/system/cpu/cpu2/topology/physical_package_id
0
/ # cat /sys/devices/system/cpu/cpu2/topology/core_siblings_list
0-7
Signed-off-by: Atish Patra <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
hw/riscv/virt.c | 22 ++++++++++++++++++++--
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 487f61404b21..28d96daf8c5b 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -191,6 +191,7 @@ static void *create_fdt(RISCVVirtState *s, const struct
MemmapEntry *memmap,
for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
int cpu_phandle = phandle++;
+ int intc_phandle;
nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu);
char *isa = riscv_isa_string(&s->soc.harts[cpu]);
@@ -203,9 +204,12 @@ static void *create_fdt(RISCVVirtState *s, const struct
MemmapEntry *memmap,
qemu_fdt_setprop_string(fdt, nodename, "status", "okay");
qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu);
qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu");
+ qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle);
+ qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle);
+ intc_phandle = phandle++;
qemu_fdt_add_subnode(fdt, intc);
- qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle);
- qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle);
+ qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle);
+ qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle);
qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc");
qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0);
qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1);
@@ -214,6 +218,20 @@ static void *create_fdt(RISCVVirtState *s, const struct
MemmapEntry *memmap,
g_free(nodename);
}
+ /* Add cpu-topology node */
+ qemu_fdt_add_subnode(fdt, "/cpus/cpu-map");
+ qemu_fdt_add_subnode(fdt, "/cpus/cpu-map/cluster0");
+ for (cpu = s->soc.num_harts - 1; cpu >= 0; cpu--) {
+ char *core_nodename = g_strdup_printf("/cpus/cpu-map/cluster0/core%d",
+ cpu);
+ char *cpu_nodename = g_strdup_printf("/cpus/cpu@%d", cpu);
+ uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, cpu_nodename);
+ qemu_fdt_add_subnode(fdt, core_nodename);
+ qemu_fdt_setprop_cell(fdt, core_nodename, "cpu", intc_phandle);
+ g_free(core_nodename);
+ g_free(cpu_nodename);
+ }
+
cells = g_new0(uint32_t, s->soc.num_harts * 4);
for (cpu = 0; cpu < s->soc.num_harts; cpu++) {
nodename =
--
2.21.0
- [Qemu-riscv] [PULL 08/34] RISC-V: Check PMP during Page Table Walks, (continued)
- [Qemu-riscv] [PULL 08/34] RISC-V: Check PMP during Page Table Walks, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 09/34] RISC-V: Fix a PMP bug where it succeeds even if PMP entry is off, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 17/34] qemu-deprecated.texi: Deprecate the RISC-V privledge spec 1.09.1, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 18/34] target/riscv: Require either I or E base extension, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 16/34] target/riscv: Set privledge spec 1.11.0 as default, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 22/34] RISC-V: Add support for the Zicsr extension, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 24/34] RISC-V: Update syscall list for 32-bit support., Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 26/34] disas/riscv: Disassemble reserved compressed encodings as illegal, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 20/34] target/riscv: Add support for disabling/enabling Counters, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 23/34] RISC-V: Clear load reservations on context switch and SC, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 25/34] riscv: virt: Add cpu-topology DT node.,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 28/34] riscv: sifive_u: Do not create hard-coded phandles in DT, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 27/34] disas/riscv: Fix `rdinstreth` constraint, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 29/34] riscv: sifive_u: Update the plic hart config to support multicore, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 32/34] hw/riscv: Extend the kernel loading support, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 30/34] hw/riscv: Split out the boot functions, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 31/34] hw/riscv: Add support for loading a firmware, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 34/34] hw/riscv: Load OpenSBI as the default firmware, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 33/34] roms: Add OpenSBI version 0.3, Palmer Dabbelt, 2019/06/28