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[Qemu-riscv] [PULL 03/34] target/riscv: Fix PMP range boundary address b
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 03/34] target/riscv: Fix PMP range boundary address bug |
Date: |
Fri, 28 Jun 2019 10:31:56 -0700 |
From: Dayeol Lee <address@hidden>
A wrong address is passed to `pmp_is_in_range` while checking if a
memory access is within a PMP range.
Since the ending address of the pmp range (i.e., pmp_state.addr[i].ea)
is set to the last address in the range (i.e., pmp base + pmp size - 1),
memory accesses containg the last address in the range will always fail.
For example, assume that a PMP range is 4KB from 0x87654000 such that
the last address within the range is 0x87654fff.
1-byte access to 0x87654fff should be considered to be fully inside the
PMP range.
However the access now fails and complains partial inclusion because
pmp_is_in_range(env, i, addr + size) returns 0 whereas
pmp_is_in_range(env, i, addr) returns 1.
Signed-off-by: Dayeol Lee <address@hidden>
Reviewed-by: Alistair Francis <address@hidden>
Reviewed-by: Michael Clark <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index fed1c3c0301b..e0fe2064074a 100644
--- a/target/riscv/pmp.c
+++ b/target/riscv/pmp.c
@@ -245,7 +245,7 @@ bool pmp_hart_has_privs(CPURISCVState *env, target_ulong
addr,
from low to high */
for (i = 0; i < MAX_RISCV_PMPS; i++) {
s = pmp_is_in_range(env, i, addr);
- e = pmp_is_in_range(env, i, addr + size);
+ e = pmp_is_in_range(env, i, addr + size - 1);
/* partially inside */
if ((s + e) == 1) {
--
2.21.0
- [Qemu-riscv] [PULL] RISC-V Patches for the 4.1 Soft Freeze, Part 2 v2, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 01/34] target/riscv: Allow setting ISA extensions via CPU props, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 02/34] sifive_prci: Read and write PRCI registers, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 03/34] target/riscv: Fix PMP range boundary address bug,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 05/34] RISC-V: Only Check PMP if MMU translation succeeds, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 04/34] target/riscv: Implement riscv_cpu_unassigned_access, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 10/34] RISC-V: Fix a PMP check with the correct access size, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 06/34] RISC-V: Raise access fault exceptions on PMP violations, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 07/34] RISC-V: Check for the effective memory privilege mode during PMP checks, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 12/34] RISC-V: Fix a memory leak when realizing a sifive_e, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 14/34] target/riscv: Add the privledge spec version 1.11.0, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 11/34] riscv: virt: Correct pci "bus-range" encoding, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 15/34] target/riscv: Add the mcountinhibit CSR, Palmer Dabbelt, 2019/06/28
- [Qemu-riscv] [PULL 13/34] target/riscv: Restructure deprecatd CPUs, Palmer Dabbelt, 2019/06/28