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Re: [Qemu-riscv] [PATCH for-4.1 4/8] target/riscv: Merge argument decode


From: Palmer Dabbelt
Subject: Re: [Qemu-riscv] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti
Date: Tue, 30 Apr 2019 18:01:53 -0700 (PDT)

On Thu, 25 Apr 2019 09:50:41 PDT (-0700), address@hidden wrote:
On 4/25/19 9:04 AM, Palmer Dabbelt wrote:
 # *** RV64C Standard Extension (Quadrant 2) ***
-c_slli            000 .  .....  ..... 10 @c_shift2
+slli              000 .  .....  ..... 10 @c_shift2

This is another one where rd=0 is illegal in the compressed ISA, but again we
don't appear to handle these correctly before the cleanups.

I see "HINT, rd=0" in the 2.2 documentation for this case.

Looks like you're right -- I was assuming the "rd != 0" to mean that it was an
illegal instruction, but I just confirmed with Andrew that it's legal.  In this
case (and probably the others I mentioned), I think QEMU is correct already.



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