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[Qemu-riscv] [PATCH v1 5/8] target/riscv: Allow setting mstatus virtulis
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 5/8] target/riscv: Allow setting mstatus virtulisation bits |
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Date: |
Sat, 20 Apr 2019 02:27:18 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/csr.c | 17 ++++++++---------
1 file changed, 8 insertions(+), 9 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index f9d8d150e0..e6d68a9956 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -290,7 +290,6 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
{
target_ulong mstatus = env->mstatus;
target_ulong mask = 0;
- target_ulong mpp = get_field(val, MSTATUS_MPP);
/* flush tlb on mstatus fields that affect VM */
if (env->priv_ver <= PRIV_VERSION_1_09_1) {
@@ -305,7 +304,7 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
MSTATUS_VM : 0);
}
if (env->priv_ver >= PRIV_VERSION_1_10_0) {
- if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP |
+ if ((val ^ mstatus) & (MSTATUS_MXR | MSTATUS_MPP | MSTATUS_MPV |
MSTATUS_MPRV | MSTATUS_SUM)) {
tlb_flush(CPU(riscv_env_get_cpu(env)));
}
@@ -313,13 +312,13 @@ static int write_mstatus(CPURISCVState *env, int csrno,
target_ulong val)
MSTATUS_SPP | MSTATUS_FS | MSTATUS_MPRV | MSTATUS_SUM |
MSTATUS_MPP | MSTATUS_MXR | MSTATUS_TVM | MSTATUS_TSR |
MSTATUS_TW;
- }
-
- /* silenty discard mstatus.mpp writes for unsupported modes */
- if (mpp == PRV_H ||
- (!riscv_has_ext(env, RVS) && mpp == PRV_S) ||
- (!riscv_has_ext(env, RVU) && mpp == PRV_U)) {
- mask &= ~MSTATUS_MPP;
+#if defined(TARGET_RISCV64)
+ /*
+ * RV32: MPV and MTL are not in mstatus. The current plan is to
+ * add them to mstatush. For now, we just don't support it.
+ */
+ mask |= MSTATUS_MPP | MSTATUS_MPV;
+#endif
}
mstatus = (mstatus & ~mask) | (val & mask);
--
2.21.0
- [Qemu-riscv] [PATCH v1 0/8] RISC-V: Add some prep patches for the Hypervisor, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 1/8] target/riscv: Mark privilege level 2 as reserved, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 2/8] target/riscv: Trigger interrupt on MIP update asynchronously, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 3/8] target/riscv: Improve the scause logic, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 5/8] target/riscv: Allow setting mstatus virtulisation bits,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 4/8] target/riscv: Add the MPV and MTL mstatus bits, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 6/8] target/riscv: Add Hypervisor CSR macros, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 7/8] target/riscv: Add the HSTATUS register masks, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 8/8] target/riscv: Add the HGATP register masks, Alistair Francis, 2019/04/19