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[Qemu-riscv] [PATCH v1 0/8] RISC-V: Add some prep patches for the Hyperv
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH v1 0/8] RISC-V: Add some prep patches for the Hypervisor |
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Date: |
Sat, 20 Apr 2019 02:26:37 +0000 |
Alistair Francis (8):
target/riscv: Mark privilege level 2 as reserved
target/riscv: Trigger interrupt on MIP update asynchronously
target/riscv: Improve the scause logic
target/riscv: Add the MPV and MTL mstatus bits
target/riscv: Allow setting mstatus virtulisation bits
target/riscv: Add Hypervisor CSR macros
target/riscv: Add the HSTATUS register masks
target/riscv: Add the HGATP register masks
target/riscv/cpu_bits.h | 45 +++++++++++++++++++++++++++++++++------
target/riscv/cpu_helper.c | 35 ++++++++++++++++++++++++------
target/riscv/csr.c | 19 +++++++----------
3 files changed, 74 insertions(+), 25 deletions(-)
--
2.21.0
- [Qemu-riscv] [PATCH v1 0/8] RISC-V: Add some prep patches for the Hypervisor,
Alistair Francis <=
- [Qemu-riscv] [PATCH v1 1/8] target/riscv: Mark privilege level 2 as reserved, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 2/8] target/riscv: Trigger interrupt on MIP update asynchronously, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 3/8] target/riscv: Improve the scause logic, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 5/8] target/riscv: Allow setting mstatus virtulisation bits, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 4/8] target/riscv: Add the MPV and MTL mstatus bits, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 6/8] target/riscv: Add Hypervisor CSR macros, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 7/8] target/riscv: Add the HSTATUS register masks, Alistair Francis, 2019/04/19
- [Qemu-riscv] [PATCH v1 8/8] target/riscv: Add the HGATP register masks, Alistair Francis, 2019/04/19