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[Qemu-riscv] [PATCH for 4.1 v3 5/6] target/riscv: Remove the generic no
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From: |
Alistair Francis |
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Subject: |
[Qemu-riscv] [PATCH for 4.1 v3 5/6] target/riscv: Remove the generic no MMU CPUs |
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Date: |
Wed, 10 Apr 2019 23:10:52 +0000 |
These can now be specified via the command line so we no longer need
these.
Signed-off-by: Alistair Francis <address@hidden>
---
target/riscv/cpu.c | 2 --
target/riscv/cpu.h | 2 --
2 files changed, 4 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index c792bacd24..9ba77a1983 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -586,13 +586,11 @@ static const TypeInfo riscv_cpu_type_infos[] = {
#if defined(TARGET_RISCV32)
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_09_1, rv32gcsu_priv1_09_1_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV32GCSU_V1_10_0, rv32gcsu_priv1_10_0_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV32IMACU_NOMMU, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E31, rv32imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U34, rv32gcsu_priv1_10_0_cpu_init)
#elif defined(TARGET_RISCV64)
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_09_1, rv64gcsu_priv1_09_1_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_RV64GCSU_V1_10_0, rv64gcsu_priv1_10_0_cpu_init),
- DEFINE_CPU(TYPE_RISCV_CPU_RV64IMACU_NOMMU, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_E51, rv64imacu_nommu_cpu_init),
DEFINE_CPU(TYPE_RISCV_CPU_SIFIVE_U54, rv64gcsu_priv1_10_0_cpu_init)
#endif
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index bc877d8107..6806f602b5 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -51,10 +51,8 @@
#define TYPE_RISCV_CPU_GEN RISCV_CPU_TYPE_NAME("rv*")
#define TYPE_RISCV_CPU_RV32GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.9.1")
#define TYPE_RISCV_CPU_RV32GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv32gcsu-v1.10.0")
-#define TYPE_RISCV_CPU_RV32IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv32imacu-nommu")
#define TYPE_RISCV_CPU_RV64GCSU_V1_09_1 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.9.1")
#define TYPE_RISCV_CPU_RV64GCSU_V1_10_0 RISCV_CPU_TYPE_NAME("rv64gcsu-v1.10.0")
-#define TYPE_RISCV_CPU_RV64IMACU_NOMMU RISCV_CPU_TYPE_NAME("rv64imacu-nommu")
#define TYPE_RISCV_CPU_SIFIVE_E31 RISCV_CPU_TYPE_NAME("sifive-e31")
#define TYPE_RISCV_CPU_SIFIVE_E51 RISCV_CPU_TYPE_NAME("sifive-e51")
#define TYPE_RISCV_CPU_SIFIVE_U34 RISCV_CPU_TYPE_NAME("sifive-u34")
--
2.21.0
[Qemu-riscv] [PATCH for 4.1 v3 3/6] target/riscv: Create settable CPU properties, Alistair Francis, 2019/04/10
[Qemu-riscv] [PATCH for 4.1 v3 1/6] linux-user/riscv: Add the CPU type as a comment, Alistair Francis, 2019/04/10
[Qemu-riscv] [PATCH for 4.1 v3 4/6] riscv: virt: Allow specifying a CPU via commandline, Alistair Francis, 2019/04/10
[Qemu-riscv] [PATCH for 4.1 v3 5/6] target/riscv: Remove the generic no MMU CPUs,
Alistair Francis <=
[Qemu-riscv] [PATCH for 4.1 v3 2/6] target/riscv: Fall back to generating a RISC-V CPU, Alistair Francis, 2019/04/10
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3 2/6] target/riscv: Fall back to generating a RISC-V CPU, Igor Mammedov, 2019/04/11
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3 2/6] target/riscv: Fall back to generating a RISC-V CPU, Alistair Francis, 2019/04/11
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3 2/6] target/riscv: Fall back to generating a RISC-V CPU, Igor Mammedov, 2019/04/12
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3 2/6] target/riscv: Fall back to generating a RISC-V CPU, Alistair Francis, 2019/04/12
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3 2/6] target/riscv: Fall back to generating a RISC-V CPU, Igor Mammedov, 2019/04/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3 2/6] target/riscv: Fall back to generating a RISC-V CPU, Alistair Francis, 2019/04/15
- Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3 2/6] target/riscv: Fall back to generating a RISC-V CPU, Igor Mammedov, 2019/04/16
Re: [Qemu-riscv] [Qemu-devel] [PATCH for 4.1 v3 2/6] target/riscv: Fall back to generating a RISC-V CPU, Daniel P . Berrangé, 2019/04/16