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[Qemu-riscv] [PATCH for-4.1 0/8] target/riscv: decodetree improvments
From: |
Richard Henderson |
Subject: |
[Qemu-riscv] [PATCH for-4.1 0/8] target/riscv: decodetree improvments |
Date: |
Mon, 1 Apr 2019 10:11:47 +0700 |
There's new support in decodetree for pattern groups.
I believe that patch 5, or something close to it, was
posted as an RFC as part of the original pattern group
patch set, but this cleans that up further.
r~
Richard Henderson (8):
target/riscv: Name the argument sets for all of insn32 formats
target/riscv: Use --static-decode for decodetree
target/riscv: Merge argument sets for insn32 and insn16
target/riscv: Merge argument decode for RVC shifti
target/riscv: Use pattern groups in insn16.decode
target/riscv: Split RVC32 and RVC64 insns into separate files
target/riscv: Split gen_arith_imm into functional and temp
target/riscv: Remove spaces from register names
target/riscv/cpu.c | 16 +-
target/riscv/insn_trans/trans_rvc.inc.c | 347 ------------------------
target/riscv/insn_trans/trans_rvi.inc.c | 20 +-
target/riscv/translate.c | 40 ++-
target/riscv/Makefile.objs | 15 +-
target/riscv/insn16-32.decode | 28 ++
target/riscv/insn16-64.decode | 30 ++
target/riscv/insn16.decode | 154 ++++++-----
target/riscv/insn32.decode | 10 +-
9 files changed, 205 insertions(+), 455 deletions(-)
delete mode 100644 target/riscv/insn_trans/trans_rvc.inc.c
create mode 100644 target/riscv/insn16-32.decode
create mode 100644 target/riscv/insn16-64.decode
--
2.17.1
- [Qemu-riscv] [PATCH for-4.1 0/8] target/riscv: decodetree improvments,
Richard Henderson <=
- [Qemu-riscv] [PATCH for-4.1 1/8] target/riscv: Name the argument sets for all of insn32 formats, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 2/8] target/riscv: Use --static-decode for decodetree, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 4/8] target/riscv: Merge argument decode for RVC shifti, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 3/8] target/riscv: Merge argument sets for insn32 and insn16, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 5/8] target/riscv: Use pattern groups in insn16.decode, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 6/8] target/riscv: Split RVC32 and RVC64 insns into separate files, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 7/8] target/riscv: Split gen_arith_imm into functional and temp, Richard Henderson, 2019/03/31
- [Qemu-riscv] [PATCH for-4.1 8/8] target/riscv: Remove spaces from register names, Richard Henderson, 2019/03/31