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[Qemu-riscv] [PULL 06/34] target/riscv: Convert RVXI fence insns to deco
From: |
Palmer Dabbelt |
Subject: |
[Qemu-riscv] [PULL 06/34] target/riscv: Convert RVXI fence insns to decodetree |
Date: |
Fri, 1 Mar 2019 13:49:17 -0800 |
From: Bastian Koppelmann <address@hidden>
Acked-by: Alistair Francis <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
Signed-off-by: Palmer Dabbelt <address@hidden>
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvi.inc.c | 19 +++++++++++++++++++
target/riscv/translate.c | 12 ------------
3 files changed, 21 insertions(+), 12 deletions(-)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index 1f5bf1f6f97d..804b721ca51e 100644
--- a/target/riscv/insn32.decode
+++ b/target/riscv/insn32.decode
@@ -82,3 +82,5 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
sra 0100000 ..... ..... 101 ..... 0110011 @r
or 0000000 ..... ..... 110 ..... 0110011 @r
and 0000000 ..... ..... 111 ..... 0110011 @r
+fence ---- pred:4 succ:4 ----- 000 ----- 0001111
+fence_i ---- ---- ---- ----- 001 ----- 0001111
diff --git a/target/riscv/insn_trans/trans_rvi.inc.c
b/target/riscv/insn_trans/trans_rvi.inc.c
index 136fa54d0655..973d6371df85 100644
--- a/target/riscv/insn_trans/trans_rvi.inc.c
+++ b/target/riscv/insn_trans/trans_rvi.inc.c
@@ -318,3 +318,22 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
return true;
}
#endif
+
+static bool trans_fence(DisasContext *ctx, arg_fence *a)
+{
+ /* FENCE is a full memory barrier. */
+ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
+ return true;
+}
+
+static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
+{
+ /*
+ * FENCE_I is a no-op in QEMU,
+ * however we need to end the translation block
+ */
+ tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
+ tcg_gen_exit_tb(NULL, 0);
+ ctx->base.is_jmp = DISAS_NORETURN;
+ return true;
+}
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 1ae84dcd5992..f720746cb791 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1950,18 +1950,6 @@ static void decode_RV32_64G(DisasContext *ctx)
gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2,
GET_RM(ctx->opcode));
break;
- case OPC_RISC_FENCE:
- if (ctx->opcode & 0x1000) {
- /* FENCE_I is a no-op in QEMU,
- * however we need to end the translation block */
- tcg_gen_movi_tl(cpu_pc, ctx->pc_succ_insn);
- tcg_gen_exit_tb(NULL, 0);
- ctx->base.is_jmp = DISAS_NORETURN;
- } else {
- /* FENCE is a full memory barrier. */
- tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC);
- }
- break;
case OPC_RISC_SYSTEM:
gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);
--
2.18.1
- [Qemu-riscv] [PULL] target/riscv: Convert to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 03/34] target/riscv: Convert RV32I load/store insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 02/34] target/riscv: Convert RVXI branch insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 04/34] target/riscv: Convert RV64I load/store insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 01/34] target/riscv: Activate decodetree and implemnt LUI & AUIPC, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 05/34] target/riscv: Convert RVXI arithmetic insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 06/34] target/riscv: Convert RVXI fence insns to decodetree,
Palmer Dabbelt <=
- [Qemu-riscv] [PULL 07/34] target/riscv: Convert RVXI csr insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 10/34] target/riscv: Convert RV64A insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 09/34] target/riscv: Convert RV32A insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 08/34] target/riscv: Convert RVXM insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 20/34] target/riscv: Remove manual decoding from gen_branch(), Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 12/34] target/riscv: Convert RV64F insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 24/34] target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 15/34] target/riscv: Convert RV priv insns to decodetree, Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 21/34] target/riscv: Remove manual decoding from gen_load(), Palmer Dabbelt, 2019/03/01
- [Qemu-riscv] [PULL 22/34] target/riscv: Remove manual decoding from gen_store(), Palmer Dabbelt, 2019/03/01