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[Qemu-riscv] [RFC v2 11/24] riscv: tcg-target: Add the mov and movi inst
From: |
Alistair Francis |
Subject: |
[Qemu-riscv] [RFC v2 11/24] riscv: tcg-target: Add the mov and movi instruction |
Date: |
Tue, 27 Nov 2018 21:08:16 +0000 |
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
---
tcg/riscv/tcg-target.inc.c | 78 ++++++++++++++++++++++++++++++++++++++
1 file changed, 78 insertions(+)
diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c
index 9c48679f11..e5a07b146f 100644
--- a/tcg/riscv/tcg-target.inc.c
+++ b/tcg/riscv/tcg-target.inc.c
@@ -434,6 +434,84 @@ static void patch_reloc(tcg_insn_unit *code_ptr, int type,
}
}
+/*
+ * TCG intrinsics
+ */
+
+static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
+{
+ if (ret == arg) {
+ return;
+ }
+ switch (type) {
+ case TCG_TYPE_I32:
+ case TCG_TYPE_I64:
+ tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+}
+
+static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd,
+ tcg_target_long val)
+{
+#if TCG_TARGET_REG_BITS == 64
+ tcg_target_long lo = sextract64(val, 0, 12);
+#else
+ tcg_target_long lo = sextract32(val, 0, 12);
+#endif
+ tcg_target_long hi = val - lo;
+ int shift;
+ tcg_target_long tmp;
+
+ RISCVInsn add32_op = TCG_TARGET_REG_BITS == 64 ? OPC_ADDIW : OPC_ADDI;
+
+#if TCG_TARGET_REG_BITS == 64
+ ptrdiff_t offset = tcg_pcrel_diff(s, (void *)val);
+#endif
+
+ if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) {
+ tcg_out_opc_upper(s, OPC_LUI, rd, hi);
+ if (lo != 0) {
+ tcg_out_opc_imm(s, add32_op, rd, rd, lo);
+ }
+
+ return;
+ }
+
+ /* We can only be here if TCG_TARGET_REG_BITS != 32 */
+ if (offset == sextract64(offset, 1, 31) << 1) {
+ tcg_out_opc_upper(s, OPC_AUIPC, rd, 0);
+ tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0);
+ reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val);
+ return;
+ }
+
+ shift = ctz64(val);
+ tmp = val >> shift;
+
+ if (tmp == sextract64(tmp, 0, 12)) {
+ tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, 1);
+ tcg_out_opc_imm(s, OPC_SLLI, rd, rd, ctz64(val));
+ } else if (!(val >> 31 == 0 || val >> 31 == -1)) {
+ shift = ctz64(hi);
+ hi >>= shift;
+ tcg_out_movi(s, type, rd, hi);
+ tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift);
+ if (lo != 0) {
+ tcg_out_opc_imm(s, OPC_ADDI, rd, rd, lo);
+ }
+ } else {
+ if (hi != 0) {
+ tcg_out_opc_upper(s, OPC_LUI, rd, hi);
+ }
+ if (lo != 0) {
+ tcg_out_opc_imm(s, add32_op, rd, hi == 0 ? TCG_REG_ZERO : rd, lo);
+ }
+ }
+}
+
void tb_target_set_jmp_target(uintptr_t tc_ptr, uintptr_t jmp_addr,
uintptr_t addr)
{
--
2.19.1
- [Qemu-riscv] [RFC v2 05/24] riscv: Add the tcg-target header file, (continued)
- [Qemu-riscv] [RFC v2 05/24] riscv: Add the tcg-target header file, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 06/24] riscv: Add the tcg target registers, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 07/24] riscv: tcg-target: Add support for the constraints, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 08/24] riscv: tcg-target: Add the immediate encoders, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 10/24] riscv: tcg-target: Add the relocation functions, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 09/24] riscv: tcg-target: Add the instruction emitters, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 11/24] riscv: tcg-target: Add the mov and movi instruction,
Alistair Francis <=
- [Qemu-riscv] [RFC v2 12/24] riscv: tcg-target: Add the extract instructions, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 13/24] riscv: tcg-target: Add the out load and store instructions, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 14/24] riscv: tcg-target: Add branch and jump instructions, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 15/24] riscv: tcg-target: Add slowpath load and store instructions, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 16/24] riscv: tcg-target: Add direct load and store instructions, Alistair Francis, 2018/11/27
- [Qemu-riscv] [RFC v2 17/24] riscv: tcg-target: Add the out op decoder, Alistair Francis, 2018/11/27