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[PATCH 40/45] target/hppa: Adjust priv for B,GATE at runtime
From: |
Richard Henderson |
Subject: |
[PATCH 40/45] target/hppa: Adjust priv for B,GATE at runtime |
Date: |
Wed, 24 Apr 2024 17:00:18 -0700 |
Do not compile in the priv change based on the first
translation; look up the PTE at execution time.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/cpu.h | 1 -
target/hppa/helper.h | 1 +
target/hppa/mem_helper.c | 34 +++++++++++++++++++++++++++-------
target/hppa/translate.c | 36 +++++++++++++++++++-----------------
4 files changed, 47 insertions(+), 25 deletions(-)
diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h
index 5f3e99cdc4..8523f22452 100644
--- a/target/hppa/cpu.h
+++ b/target/hppa/cpu.h
@@ -386,7 +386,6 @@ void hppa_cpu_do_transaction_failed(CPUState *cs, hwaddr
physaddr,
extern const MemoryRegionOps hppa_io_eir_ops;
extern const VMStateDescription vmstate_hppa_cpu;
void hppa_cpu_alarm_timer(void *);
-int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr);
#endif
G_NORETURN void hppa_dynamic_excp(CPUHPPAState *env, int excp, uintptr_t ra);
diff --git a/target/hppa/helper.h b/target/hppa/helper.h
index c12b48a04a..de411923d9 100644
--- a/target/hppa/helper.h
+++ b/target/hppa/helper.h
@@ -86,6 +86,7 @@ DEF_HELPER_1(halt, noreturn, env)
DEF_HELPER_1(reset, noreturn, env)
DEF_HELPER_1(rfi, void, env)
DEF_HELPER_1(rfi_r, void, env)
+DEF_HELPER_FLAGS_2(b_gate_priv, TCG_CALL_NO_WG, i64, env, i64)
DEF_HELPER_FLAGS_2(write_interval_timer, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(write_eirr, TCG_CALL_NO_RWG, void, env, tl)
DEF_HELPER_FLAGS_2(swap_system_mask, TCG_CALL_NO_RWG, tl, env, tl)
diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c
index 3ef9e80064..6756d36dae 100644
--- a/target/hppa/mem_helper.c
+++ b/target/hppa/mem_helper.c
@@ -690,13 +690,6 @@ target_ulong HELPER(lpa)(CPUHPPAState *env, target_ulong
addr)
return phys;
}
-/* Return the ar_type of the TLB at VADDR, or -1. */
-int hppa_artype_for_page(CPUHPPAState *env, target_ulong vaddr)
-{
- HPPATLBEntry *ent = hppa_find_tlb(env, vaddr);
- return ent ? ent->ar_type : -1;
-}
-
/*
* diag_btlb() emulates the PDC PDC_BLOCK_TLB firmware call to
* allow operating systems to modify the Block TLB (BTLB) entries.
@@ -792,3 +785,30 @@ void HELPER(diag_btlb)(CPUHPPAState *env)
break;
}
}
+
+uint64_t HELPER(b_gate_priv)(CPUHPPAState *env, uint64_t iaoq_f)
+{
+ uint64_t gva = hppa_form_gva(env, env->iasq_f, iaoq_f);
+ HPPATLBEntry *ent = hppa_find_tlb(env, gva);
+
+ if (ent == NULL) {
+ raise_exception_with_ior(env, EXCP_ITLB_MISS, GETPC(), gva, false);
+ }
+
+ /*
+ * There should be no need to check page permissions, as that will
+ * already have been done by tb_lookup via get_page_addr_code.
+ * All we need at this point is to check the ar_type.
+ *
+ * No change for non-gateway pages or for priv decrease.
+ */
+ if (ent->ar_type & 4) {
+ int old_priv = iaoq_f & 3;
+ int new_priv = ent->ar_type & 3;
+
+ if (new_priv < old_priv) {
+ iaoq_f = (iaoq_f & -4) | new_priv;
+ }
+ }
+ return iaoq_f;
+}
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index a4200742bd..3ae196490a 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -3959,6 +3959,7 @@ static bool trans_bl(DisasContext *ctx, arg_bl *a)
static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
{
int64_t disp = a->disp;
+ bool indirect = false;
/* Trap if PSW[B] is set. */
if (ctx->psw_xb & PSW_B) {
@@ -3968,24 +3969,22 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate
*a)
nullify_over(ctx);
#ifndef CONFIG_USER_ONLY
- if (ctx->tb_flags & PSW_C) {
- int type = hppa_artype_for_page(cpu_env(ctx->cs), ctx->base.pc_next);
- /* If we could not find a TLB entry, then we need to generate an
- ITLB miss exception so the kernel will provide it.
- The resulting TLB fill operation will invalidate this TB and
- we will re-translate, at which point we *will* be able to find
- the TLB entry and determine if this is in fact a gateway page. */
- if (type < 0) {
- gen_excp(ctx, EXCP_ITLB_MISS);
- return true;
- }
- /* No change for non-gateway pages or for priv decrease. */
- if (type >= 4 && type - 4 < ctx->privilege) {
- disp -= ctx->privilege;
- disp += type - 4;
- }
+ if (ctx->privilege == 0) {
+ /* Privilege cannot decrease. */
+ } else if (!(ctx->tb_flags & PSW_C)) {
+ /* With paging disabled, priv becomes 0. */
+ disp -= ctx->privilege;
} else {
- disp -= ctx->privilege; /* priv = 0 */
+ /* Adjust the dest offset for the privilege change from the PTE. */
+ TCGv_i64 off = tcg_temp_new_i64();
+
+ gen_helper_b_gate_priv(off, tcg_env,
+ tcg_constant_i64(ctx->iaoq_first
+ + ctx->iaq_f.disp));
+
+ ctx->iaq_j.base = off;
+ ctx->iaq_j.disp = disp + 8;
+ indirect = true;
}
#endif
@@ -3998,6 +3997,9 @@ static bool trans_b_gate(DisasContext *ctx, arg_b_gate *a)
save_gpr(ctx, a->l, tmp);
}
+ if (indirect) {
+ return do_ibranch(ctx, 0, false, a->n);
+ }
return do_dbranch(ctx, disp, 0, a->n);
}
--
2.34.1
- [PATCH 33/45] target/hppa: Do not mask in copy_iaoq_entry, (continued)
- [PATCH 33/45] target/hppa: Do not mask in copy_iaoq_entry, Richard Henderson, 2024/04/24
- [PATCH 35/45] target/hppa: Split PSW X and B into their own field, Richard Henderson, 2024/04/24
- [PATCH 37/45] target/hppa: Implement PSW_B, Richard Henderson, 2024/04/24
- [PATCH 38/45] target/hppa: Implement PSW_X, Richard Henderson, 2024/04/24
- [PATCH 39/45] target/hppa: Drop tlb_entry return from hppa_get_physical_address, Richard Henderson, 2024/04/24
- [PATCH 41/45] target/hppa: Implement CF_PCREL, Richard Henderson, 2024/04/24
- [PATCH 44/45] target/hppa: Log cpu state at interrupt, Richard Henderson, 2024/04/24
- [PATCH 43/45] target/hppa: Implement PSW_H, PSW_L, Richard Henderson, 2024/04/24
- [PATCH 42/45] target/hppa: Implement PSW_T, Richard Henderson, 2024/04/24
- [PATCH 45/45] target/hppa: Log cpu state on return-from-interrupt, Richard Henderson, 2024/04/24
- [PATCH 40/45] target/hppa: Adjust priv for B,GATE at runtime,
Richard Henderson <=