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[PATCH v11 21/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID
From: |
Zhao Liu |
Subject: |
[PATCH v11 21/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14] |
Date: |
Wed, 24 Apr 2024 23:49:29 +0800 |
CPUID[0x8000001D].EAX[bits 25:14] NumSharingCache: number of logical
processors sharing cache.
The number of logical processors sharing this cache is
NumSharingCache + 1.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[0x8000001D].EAX[bits 25:14].
Tested-by: Yongwei Ma <yongwei.ma@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
Tested-by: Babu Moger <babu.moger@amd.com>
Reviewed-by: Babu Moger <babu.moger@amd.com>
---
Changes since v7:
* Renamed max_processor_ids_for_cache() to max_thread_ids_for_cache().
* Dropped Michael/Babu's ACKed/Tested tags since the code change.
* Re-added Yongwei's Tested tag For his re-testing.
Changes since v3:
* Explained what "CPUID[0x8000001D].EAX[bits 25:14]" means in the
commit message. (Babu)
Changes since v1:
* Used cache->share_level as the parameter in
max_processor_ids_for_cache().
---
target/i386/cpu.c | 10 +---------
1 file changed, 1 insertion(+), 9 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 6ab517a59aee..369c5ee54fa6 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -478,20 +478,12 @@ static void encode_cache_cpuid8000001d(CPUCacheInfo
*cache,
uint32_t *eax, uint32_t *ebx,
uint32_t *ecx, uint32_t *edx)
{
- uint32_t num_sharing_cache;
assert(cache->size == cache->line_size * cache->associativity *
cache->partitions * cache->sets);
*eax = CACHE_TYPE(cache->type) | CACHE_LEVEL(cache->level) |
(cache->self_init ? CACHE_SELF_INIT_LEVEL : 0);
-
- /* L3 is shared among multiple cores */
- if (cache->level == 3) {
- num_sharing_cache = 1 << apicid_die_offset(topo_info);
- } else {
- num_sharing_cache = 1 << apicid_core_offset(topo_info);
- }
- *eax |= (num_sharing_cache - 1) << 14;
+ *eax |= max_thread_ids_for_cache(topo_info, cache->share_level) << 14;
assert(cache->line_size > 0);
assert(cache->partitions > 0);
--
2.34.1
- [PATCH v11 10/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB], (continued)
- [PATCH v11 10/21] i386: Split topology types of CPUID[0x1F] from the definitions of CPUID[0xB], Zhao Liu, 2024/04/24
- [PATCH v11 12/21] i386: Introduce module level cpu topology to CPUX86State, Zhao Liu, 2024/04/24
- [PATCH v11 13/21] i386: Support modules_per_die in X86CPUTopoInfo, Zhao Liu, 2024/04/24
- [PATCH v11 14/21] i386: Expose module level in CPUID[0x1F], Zhao Liu, 2024/04/24
- [PATCH v11 15/21] i386: Support module_id in X86CPUTopoIDs, Zhao Liu, 2024/04/24
- [PATCH v11 16/21] i386/cpu: Introduce module-id to X86CPU, Zhao Liu, 2024/04/24
- [PATCH v11 17/21] tests: Add test case of APIC ID for module level parsing, Zhao Liu, 2024/04/24
- [PATCH v11 18/21] hw/i386/pc: Support smp.modules for x86 PC machine, Zhao Liu, 2024/04/24
- [PATCH v11 19/21] i386: Add cache topology info in CPUCacheInfo, Zhao Liu, 2024/04/24
- [PATCH v11 20/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[4], Zhao Liu, 2024/04/24
- [PATCH v11 21/21] i386/cpu: Use CPUCacheInfo.share_level to encode CPUID[0x8000001D].EAX[bits 25:14],
Zhao Liu <=
- Re: [PATCH v11 00/21] i386: Introduce smp.modules and clean up cache topology, Philippe Mathieu-Daudé, 2024/04/25