how does the qemu emulate the "atomic" semantics on host that DOES NOT s

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how does the qemu emulate the "atomic" semantics on host that DOES NOT s

From:	tugouxp
Subject:	how does the qemu emulate the "atomic" semantics on host that DOES NOT support atomic instructions?
Date:	Tue, 9 Apr 2024 17:57:29 +0800 (CST)

Hi folks:

How does the qemu emulate the target that support "atomic" ISA, such as riscv "amo" instruction on host machine that does NOT support atomic instructions ?

is this scenario happends?

thank you!

BRs

zlcao.

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how does the qemu emulate the "atomic" semantics on host that DOES NOT support atomic instructions?, tugouxp <=
- Re: how does the qemu emulate the "atomic" semantics on host that DOES NOT support atomic instructions?, Peter Maydell, 2024/04/09
  - Re:Re: how does the qemu emulate the "atomic" semantics on host that DOES NOT support atomic instructions?, tugouxp, 2024/04/09
    - Re: Re: how does the qemu emulate the "atomic" semantics on host that DOES NOT support atomic instructions?, Peter Maydell, 2024/04/09
    - Re:Re: Re: how does the qemu emulate the "atomic" semantics on host that DOES NOT support atomic instructions?, tugouxp, 2024/04/09

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