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[PULL 66/85] target/hppa: Implement MIXH, MIXW
From: |
Richard Henderson |
Subject: |
[PULL 66/85] target/hppa: Implement MIXH, MIXW |
Date: |
Mon, 6 Nov 2023 19:03:48 -0800 |
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/hppa/insns.decode | 5 ++++
target/hppa/translate.c | 55 ++++++++++++++++++++++++++++++++++++++++
2 files changed, 60 insertions(+)
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode
index 87db726d9e..22ec07f892 100644
--- a/target/hppa/insns.decode
+++ b/target/hppa/insns.decode
@@ -233,6 +233,11 @@ hsub 000010 ..... ..... 00000001 11 0 .....
@rrr
hsub_ss 000010 ..... ..... 00000001 01 0 ..... @rrr
hsub_us 000010 ..... ..... 00000001 00 0 ..... @rrr
+mixh_l 111110 ..... ..... 1 00 00100000 ..... @rrr
+mixh_r 111110 ..... ..... 1 10 00100000 ..... @rrr
+mixw_l 111110 ..... ..... 1 00 00000000 ..... @rrr
+mixw_r 111110 ..... ..... 1 10 00000000 ..... @rrr
+
####
# Index Mem
####
diff --git a/target/hppa/translate.c b/target/hppa/translate.c
index 648c37fb28..2b471444d0 100644
--- a/target/hppa/translate.c
+++ b/target/hppa/translate.c
@@ -2891,6 +2891,61 @@ static bool trans_hsub_us(DisasContext *ctx, arg_rrr *a)
return do_multimedia(ctx, a, gen_helper_hsub_us);
}
+static void gen_mixh_l(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2)
+{
+ uint64_t mask = 0xffff0000ffff0000ull;
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(tmp, r2, mask);
+ tcg_gen_andi_i64(dst, r1, mask);
+ tcg_gen_shri_i64(tmp, tmp, 16);
+ tcg_gen_or_i64(dst, dst, tmp);
+}
+
+static bool trans_mixh_l(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_mixh_l);
+}
+
+static void gen_mixh_r(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2)
+{
+ uint64_t mask = 0x0000ffff0000ffffull;
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ tcg_gen_andi_i64(tmp, r1, mask);
+ tcg_gen_andi_i64(dst, r2, mask);
+ tcg_gen_shli_i64(tmp, tmp, 16);
+ tcg_gen_or_i64(dst, dst, tmp);
+}
+
+static bool trans_mixh_r(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_mixh_r);
+}
+
+static void gen_mixw_l(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2)
+{
+ TCGv_i64 tmp = tcg_temp_new_i64();
+
+ tcg_gen_shri_i64(tmp, r2, 32);
+ tcg_gen_deposit_i64(dst, r1, tmp, 0, 32);
+}
+
+static bool trans_mixw_l(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_mixw_l);
+}
+
+static void gen_mixw_r(TCGv_i64 dst, TCGv_i64 r1, TCGv_i64 r2)
+{
+ tcg_gen_deposit_i64(dst, r2, r1, 32, 32);
+}
+
+static bool trans_mixw_r(DisasContext *ctx, arg_rrr *a)
+{
+ return do_multimedia(ctx, a, gen_mixw_r);
+}
+
static bool trans_ld(DisasContext *ctx, arg_ldst *a)
{
if (!ctx->is_pa20 && a->size > MO_32) {
--
2.34.1
- [PULL 56/85] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections, (continued)
- [PULL 56/85] target/hppa: Remove most of the TARGET_REGISTER_BITS redirections, Richard Henderson, 2023/11/06
- [PULL 60/85] target/hppa: Replace tcg_gen_*_tl with tcg_gen_*_i64, Richard Henderson, 2023/11/06
- [PULL 62/85] target/hppa: Implement HSUB, Richard Henderson, 2023/11/06
- [PULL 58/85] target/hppa: Adjust vmstate_env for pa2.0 tlb, Richard Henderson, 2023/11/06
- [PULL 64/85] target/hppa: Implement HSHL, HSHR, Richard Henderson, 2023/11/06
- [PULL 67/85] target/hppa: Implement PERMH, Richard Henderson, 2023/11/06
- [PULL 59/85] target/hppa: Use tcg_temp_new_i64 not tcg_temp_new, Richard Henderson, 2023/11/06
- [PULL 74/85] target/hppa: Implement pa2.0 data prefetch instructions, Richard Henderson, 2023/11/06
- [PULL 63/85] target/hppa: Implement HAVG, Richard Henderson, 2023/11/06
- [PULL 70/85] target/hppa: Return zero for r0 from load_gpr, Richard Henderson, 2023/11/06
- [PULL 66/85] target/hppa: Implement MIXH, MIXW,
Richard Henderson <=
- [PULL 68/85] target/hppa: Fix interruption based on default PSW, Richard Henderson, 2023/11/06
- [PULL 69/85] target/hppa: Precompute zero into DisasContext, Richard Henderson, 2023/11/06
- [PULL 73/85] linux-user/hppa: Drop EXCP_DUMP from handled exceptions, Richard Henderson, 2023/11/06
- [PULL 72/85] hw/hppa: Translate phys addresses for the cpu, Richard Henderson, 2023/11/06
- [PULL 78/85] target/hppa: Add unwind_breg to CPUHPPAState, Richard Henderson, 2023/11/06
- [PULL 77/85] target/hppa: Clear upper bits in mtctl for pa1.x, Richard Henderson, 2023/11/06
- [PULL 75/85] target/hppa: Add pa2.0 cpu local tlb flushes, Richard Henderson, 2023/11/06
- [PULL 71/85] include/hw/elf: Remove truncating signed casts, Richard Henderson, 2023/11/06
- [PULL 65/85] target/hppa: Implement HSHLADD, HSHRADD, Richard Henderson, 2023/11/06