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[PULL 26/49] target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot
From: |
Alistair Francis |
Subject: |
[PULL 26/49] target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot |
Date: |
Tue, 7 Nov 2023 12:29:22 +1000 |
From: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
These regs were added in Linux 6.6.
Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231031205150.208405-1-dbarboza@ventanamicro.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/kvm/kvm-cpu.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c
index a11c0e4a99..78fa1fa162 100644
--- a/target/riscv/kvm/kvm-cpu.c
+++ b/target/riscv/kvm/kvm-cpu.c
@@ -229,12 +229,17 @@ static KVMCPUConfig kvm_multi_ext_cfgs[] = {
KVM_EXT_CFG("zicbom", ext_zicbom, KVM_RISCV_ISA_EXT_ZICBOM),
KVM_EXT_CFG("zicboz", ext_zicboz, KVM_RISCV_ISA_EXT_ZICBOZ),
KVM_EXT_CFG("zicntr", ext_zicntr, KVM_RISCV_ISA_EXT_ZICNTR),
+ KVM_EXT_CFG("zicsr", ext_zicsr, KVM_RISCV_ISA_EXT_ZICSR),
+ KVM_EXT_CFG("zifencei", ext_zifencei, KVM_RISCV_ISA_EXT_ZIFENCEI),
KVM_EXT_CFG("zihintpause", ext_zihintpause, KVM_RISCV_ISA_EXT_ZIHINTPAUSE),
KVM_EXT_CFG("zihpm", ext_zihpm, KVM_RISCV_ISA_EXT_ZIHPM),
+ KVM_EXT_CFG("zba", ext_zba, KVM_RISCV_ISA_EXT_ZBA),
KVM_EXT_CFG("zbb", ext_zbb, KVM_RISCV_ISA_EXT_ZBB),
+ KVM_EXT_CFG("zbs", ext_zbs, KVM_RISCV_ISA_EXT_ZBS),
KVM_EXT_CFG("ssaia", ext_ssaia, KVM_RISCV_ISA_EXT_SSAIA),
KVM_EXT_CFG("sstc", ext_sstc, KVM_RISCV_ISA_EXT_SSTC),
KVM_EXT_CFG("svinval", ext_svinval, KVM_RISCV_ISA_EXT_SVINVAL),
+ KVM_EXT_CFG("svnapot", ext_svnapot, KVM_RISCV_ISA_EXT_SVNAPOT),
KVM_EXT_CFG("svpbmt", ext_svpbmt, KVM_RISCV_ISA_EXT_SVPBMT),
};
--
2.41.0
- [PULL 15/49] target/riscv/tcg: add tcg_cpu_finalize_features(), (continued)
- [PULL 15/49] target/riscv/tcg: add tcg_cpu_finalize_features(), Alistair Francis, 2023/11/06
- [PULL 17/49] target/riscv: add riscv_cpu_accelerator_compatible(), Alistair Francis, 2023/11/06
- [PULL 20/49] target/riscv: pmp: Clear pmp/smepmp bits on reset, Alistair Francis, 2023/11/06
- [PULL 21/49] target/riscv: pmp: Ignore writes when RW=01, Alistair Francis, 2023/11/06
- [PULL 18/49] target/riscv/riscv-qmp-cmds.c: check CPU accel in query-cpu-model-expansion, Alistair Francis, 2023/11/06
- [PULL 22/49] target/riscv: add zicntr extension flag for TCG, Alistair Francis, 2023/11/06
- [PULL 19/49] Add epmp to extensions list and rename it to smepmp, Alistair Francis, 2023/11/06
- [PULL 23/49] target/riscv/kvm: add zicntr reg, Alistair Francis, 2023/11/06
- [PULL 24/49] target/riscv: add zihpm extension flag for TCG, Alistair Francis, 2023/11/06
- [PULL 25/49] target/riscv/kvm: add zihpm reg, Alistair Francis, 2023/11/06
- [PULL 26/49] target/riscv/kvm: add zicsr, zifencei, zba, zbs, svnapot,
Alistair Francis <=
- [PULL 27/49] target/riscv: correct csr_ops[CSR_MSECCFG], Alistair Francis, 2023/11/06
- [PULL 28/49] MAINTAINERS: update mail address for Weiwei Li, Alistair Francis, 2023/11/06
- [PULL 31/49] target/riscv: Add cfg property for Zvkb extension, Alistair Francis, 2023/11/06
- [PULL 30/49] target/riscv: Expose Zvkt extension property, Alistair Francis, 2023/11/06
- [PULL 32/49] target/riscv: Replace Zvbb checking by Zvkb, Alistair Francis, 2023/11/06
- [PULL 29/49] target/riscv: Add cfg property for Zvkt extension, Alistair Francis, 2023/11/06
- [PULL 33/49] target/riscv: Expose Zvkb extension property, Alistair Francis, 2023/11/06
- [PULL 34/49] target/riscv: Add cfg properties for Zvkn[c|g] extensions, Alistair Francis, 2023/11/06
- [PULL 35/49] target/riscv: Expose Zvkn[c|g] extnesion properties, Alistair Francis, 2023/11/06
- [PULL 36/49] target/riscv: Add cfg properties for Zvks[c|g] extensions, Alistair Francis, 2023/11/06