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[PULL 06/49] target/riscv: Check for async flag in case of RISCV_EXCP_SE
From: |
Alistair Francis |
Subject: |
[PULL 06/49] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST. |
Date: |
Tue, 7 Nov 2023 12:29:02 +1000 |
From: Rajnesh Kanwal <rkanwal@rivosinc.com>
RISCV_EXCP_SEMIHOST is set to 0x10, which can be a local interrupt id
as well. This change moves RISCV_EXCP_SEMIHOST to switch case so that
async flag check is performed before invoking semihosting logic.
Signed-off-by: Rajnesh Kanwal <rkanwal@rivosinc.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20231016111736.28721-3-rkanwal@rivosinc.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu_helper.c | 10 ++++------
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index 8c28241c18..aaeb1d0d5c 100644
--- a/target/riscv/cpu_helper.c
+++ b/target/riscv/cpu_helper.c
@@ -1605,15 +1605,13 @@ void riscv_cpu_do_interrupt(CPUState *cs)
target_ulong htval = 0;
target_ulong mtval2 = 0;
- if (cause == RISCV_EXCP_SEMIHOST) {
- do_common_semihosting(cs);
- env->pc += 4;
- return;
- }
-
if (!async) {
/* set tval to badaddr for traps with address information */
switch (cause) {
+ case RISCV_EXCP_SEMIHOST:
+ do_common_semihosting(cs);
+ env->pc += 4;
+ return;
case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT:
case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT:
case RISCV_EXCP_LOAD_ADDR_MIS:
--
2.41.0
- [PULL 00/49] riscv-to-apply queue, Alistair Francis, 2023/11/06
- [PULL 01/49] target/riscv: rename ext_ifencei to ext_zifencei, Alistair Francis, 2023/11/06
- [PULL 02/49] target/riscv: rename ext_icsr to ext_zicsr, Alistair Francis, 2023/11/06
- [PULL 03/49] target/riscv: rename ext_icbom to ext_zicbom, Alistair Francis, 2023/11/06
- [PULL 04/49] target/riscv: rename ext_icboz to ext_zicboz, Alistair Francis, 2023/11/06
- [PULL 05/49] target/riscv: Without H-mode mask all HS mode inturrupts in mie., Alistair Francis, 2023/11/06
- [PULL 06/49] target/riscv: Check for async flag in case of RISCV_EXCP_SEMIHOST.,
Alistair Francis <=
- [PULL 07/49] target/riscv: Set VS* bits to one in mideleg when H-Ext is enabled, Alistair Francis, 2023/11/06
- [PULL 08/49] target/riscv: Split interrupt logic from riscv_cpu_update_mip., Alistair Francis, 2023/11/06
- [PULL 09/49] target/riscv: Add M-mode virtual interrupt and IRQ filtering support., Alistair Francis, 2023/11/06
- [PULL 10/49] target/riscv: Add HS-mode virtual interrupt and IRQ filtering support., Alistair Francis, 2023/11/06
- [PULL 12/49] docs/system/riscv: update 'virt' machine core limit, Alistair Francis, 2023/11/06
- [PULL 13/49] target/riscv/kvm/kvm-cpu.c: add missing property getters(), Alistair Francis, 2023/11/06
- [PULL 11/49] linux-user/riscv: change default cpu to 'max', Alistair Francis, 2023/11/06
- [PULL 14/49] qapi,risc-v: add query-cpu-model-expansion, Alistair Francis, 2023/11/06
- [PULL 16/49] target/riscv: handle custom props in qmp_query_cpu_model_expansion, Alistair Francis, 2023/11/06
- [PULL 15/49] target/riscv/tcg: add tcg_cpu_finalize_features(), Alistair Francis, 2023/11/06