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[PULL 09/21] target/sparc: Remove DisasCompare.is_bool
From: |
Richard Henderson |
Subject: |
[PULL 09/21] target/sparc: Remove DisasCompare.is_bool |
Date: |
Sun, 5 Nov 2023 12:12:10 -0800 |
Since we're going to feed cpu_cond to another comparison, we don't
reqire a boolean value -- anything non-zero is sufficient.
Tested-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Acked-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
target/sparc/translate.c | 22 +++++++---------------
1 file changed, 7 insertions(+), 15 deletions(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 7c4fcf8326..464f1607e3 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -180,7 +180,6 @@ typedef struct DisasContext {
typedef struct {
TCGCond cond;
- bool is_bool;
TCGv c1, c2;
} DisasCompare;
@@ -1039,7 +1038,6 @@ static void gen_compare(DisasCompare *cmp, bool xcc,
unsigned int cond,
{
TCGv t1;
- cmp->is_bool = false;
cmp->c1 = t1 = tcg_temp_new();
cmp->c2 = tcg_constant_tl(0);
@@ -1104,7 +1102,6 @@ static void gen_compare(DisasCompare *cmp, bool xcc,
unsigned int cond,
case 0x5: /* ltu: C */
cmp->cond = TCG_COND_NE;
- cmp->is_bool = true;
if (TARGET_LONG_BITS == 32 || xcc) {
tcg_gen_mov_tl(t1, cpu_cc_C);
} else {
@@ -1132,7 +1129,6 @@ static void gen_compare(DisasCompare *cmp, bool xcc,
unsigned int cond,
}
if (cond & 8) {
cmp->cond = tcg_invert_cond(cmp->cond);
- cmp->is_bool = false;
}
}
@@ -1143,7 +1139,6 @@ static void gen_fcompare(DisasCompare *cmp, unsigned int
cc, unsigned int cond)
/* For now we still generate a straight boolean result. */
cmp->cond = TCG_COND_NE;
- cmp->is_bool = true;
cmp->c1 = r_dst = tcg_temp_new();
cmp->c2 = tcg_constant_tl(0);
@@ -1230,7 +1225,6 @@ static const TCGCond gen_tcg_cond_reg[8] = {
static void gen_compare_reg(DisasCompare *cmp, int cond, TCGv r_src)
{
cmp->cond = tcg_invert_cond(gen_tcg_cond_reg[cond]);
- cmp->is_bool = false;
cmp->c1 = r_src;
cmp->c2 = tcg_constant_tl(0);
}
@@ -2232,18 +2226,14 @@ static void gen_fmovs(DisasContext *dc, DisasCompare
*cmp, int rd, int rs)
{
#ifdef TARGET_SPARC64
TCGv_i32 c32, zero, dst, s1, s2;
+ TCGv_i64 c64 = tcg_temp_new_i64();
/* We have two choices here: extend the 32 bit data and use movcond_i64,
or fold the comparison down to 32 bits and use movcond_i32. Choose
the later. */
c32 = tcg_temp_new_i32();
- if (cmp->is_bool) {
- tcg_gen_extrl_i64_i32(c32, cmp->c1);
- } else {
- TCGv_i64 c64 = tcg_temp_new_i64();
- tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
- tcg_gen_extrl_i64_i32(c32, c64);
- }
+ tcg_gen_setcond_i64(cmp->cond, c64, cmp->c1, cmp->c2);
+ tcg_gen_extrl_i64_i32(c32, c64);
s1 = gen_load_fpr_F(dc, rs);
s2 = gen_load_fpr_F(dc, rd);
@@ -2445,8 +2435,10 @@ static bool advance_jump_cond(DisasContext *dc,
DisasCompare *cmp,
dc->jump_pc[0] = dest;
dc->jump_pc[1] = npc + 4;
dc->npc = JUMP_PC;
- if (cmp->is_bool) {
- tcg_gen_mov_tl(cpu_cond, cmp->c1);
+
+ /* The condition for cpu_cond is always NE -- normalize. */
+ if (cmp->cond == TCG_COND_NE) {
+ tcg_gen_xor_tl(cpu_cond, cmp->c1, cmp->c2);
} else {
tcg_gen_setcond_tl(cmp->cond, cpu_cond, cmp->c1, cmp->c2);
}
--
2.34.1
- [PULL 00/21] target/sparc: Cleanup condition codes, Richard Henderson, 2023/11/05
- [PULL 01/21] target/sparc: Introduce cpu_put_psr_icc, Richard Henderson, 2023/11/05
- [PULL 03/21] target/sparc: Remove CC_OP_LOGIC, Richard Henderson, 2023/11/05
- [PULL 02/21] target/sparc: Split psr and xcc into components, Richard Henderson, 2023/11/05
- [PULL 06/21] target/sparc: Remove CC_OP_SUB, CC_OP_SUBX, CC_OP_TSUB, Richard Henderson, 2023/11/05
- [PULL 05/21] target/sparc: Remove CC_OP_ADD, CC_OP_ADDX, CC_OP_TADD, Richard Henderson, 2023/11/05
- [PULL 07/21] target/sparc: Remove CC_OP_TADDTV, CC_OP_TSUBTV, Richard Henderson, 2023/11/05
- [PULL 09/21] target/sparc: Remove DisasCompare.is_bool,
Richard Henderson <=
- [PULL 08/21] target/sparc: Remove CC_OP leftovers, Richard Henderson, 2023/11/05
- [PULL 10/21] target/sparc: Change DisasCompare.c2 to int, Richard Henderson, 2023/11/05
- [PULL 11/21] target/sparc: Always copy conditions into a new temporary, Richard Henderson, 2023/11/05
- [PULL 12/21] target/sparc: Do flush_cond in advance_jump_cond, Richard Henderson, 2023/11/05
- [PULL 13/21] target/sparc: Merge gen_branch2 into advance_pc, Richard Henderson, 2023/11/05
- [PULL 14/21] target/sparc: Merge advance_jump_uncond_{never, always} into advance_jump_cond, Richard Henderson, 2023/11/05
- [PULL 16/21] target/sparc: Merge gen_op_next_insn into only caller, Richard Henderson, 2023/11/05
- [PULL 17/21] target/sparc: Record entire jump condition in DisasContext, Richard Henderson, 2023/11/05
- [PULL 15/21] target/sparc: Pass displacement to advance_jump_cond, Richard Henderson, 2023/11/05
- [PULL 04/21] target/sparc: Remove CC_OP_DIV, Richard Henderson, 2023/11/05