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[PATCH v3 02/42] target/arm: Add is_secure parameter to get_phys_addr_lp
From: |
Richard Henderson |
Subject: |
[PATCH v3 02/42] target/arm: Add is_secure parameter to get_phys_addr_lpae |
Date: |
Sat, 1 Oct 2022 09:22:38 -0700 |
Remove the use of regime_is_secure from get_phys_addr_lpae,
using the new parameter instead.
Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: Update to use s2walk_secure.
---
target/arm/ptw.c | 20 ++++++++++----------
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/arm/ptw.c b/target/arm/ptw.c
index b8c494ad9f..b7c999ffce 100644
--- a/target/arm/ptw.c
+++ b/target/arm/ptw.c
@@ -16,8 +16,8 @@
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- bool s1_is_el0, GetPhysAddrResult *result,
- ARMMMUFaultInfo *fi)
+ bool is_secure, bool s1_is_el0,
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
__attribute__((nonnull));
/* This mapping is common between ID_AA64MMFR0.PARANGE and TCR_ELx.{I}PS. */
@@ -207,8 +207,8 @@ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx
mmu_idx,
GetPhysAddrResult s2 = {};
int ret;
- ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx, false,
- &s2, fi);
+ ret = get_phys_addr_lpae(env, addr, MMU_DATA_LOAD, s2_mmu_idx,
+ *is_secure, false, &s2, fi);
if (ret) {
assert(fi->type != ARMFault_None);
fi->s2addr = addr;
@@ -965,8 +965,8 @@ static bool check_s2_mmu_setup(ARMCPU *cpu, bool is_aa64,
int level,
*/
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
- bool s1_is_el0, GetPhysAddrResult *result,
- ARMMMUFaultInfo *fi)
+ bool is_secure, bool s1_is_el0,
+ GetPhysAddrResult *result, ARMMMUFaultInfo *fi)
{
ARMCPU *cpu = env_archcpu(env);
/* Read an LPAE long-descriptor translation table. */
@@ -1183,7 +1183,7 @@ static bool get_phys_addr_lpae(CPUARMState *env, uint64_t
address,
* remain non-secure. We implement this by just ORing in the NSTable/NS
* bits at each step.
*/
- tableattrs = regime_is_secure(env, mmu_idx) ? 0 : (1 << 4);
+ tableattrs = is_secure ? 0 : (1 << 4);
for (;;) {
uint64_t descriptor;
bool nstable;
@@ -2337,7 +2337,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
memset(result, 0, sizeof(*result));
ret = get_phys_addr_lpae(env, ipa, access_type, s2_mmu_idx,
- is_el0, result, fi);
+ s2walk_secure, is_el0, result, fi);
fi->s2addr = ipa;
/* Combine the S1 and S2 perms. */
@@ -2505,8 +2505,8 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
}
if (regime_using_lpae_format(env, mmu_idx)) {
- return get_phys_addr_lpae(env, address, access_type, mmu_idx, false,
- result, fi);
+ return get_phys_addr_lpae(env, address, access_type, mmu_idx,
+ is_secure, false, result, fi);
} else if (regime_sctlr(env, mmu_idx) & SCTLR_XP) {
return get_phys_addr_v6(env, address, access_type, mmu_idx,
is_secure, result, fi);
--
2.34.1
- [PATCH v3 00/42] target/arm: Implement FEAT_HAFDBS, Richard Henderson, 2022/10/01
- [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Richard Henderson, 2022/10/01
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Peter Maydell, 2022/10/06
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Richard Henderson, 2022/10/06
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Peter Maydell, 2022/10/06
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Richard Henderson, 2022/10/06
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Peter Maydell, 2022/10/06
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Richard Henderson, 2022/10/06
- Re: [PATCH v3 01/42] target/arm: Split s2walk_secure from ipa_secure in get_phys_addr, Peter Maydell, 2022/10/07
[PATCH v3 02/42] target/arm: Add is_secure parameter to get_phys_addr_lpae,
Richard Henderson <=
[PATCH v3 03/42] target/arm: Fix S2 disabled check in S1_ptw_translate, Richard Henderson, 2022/10/01
[PATCH v3 04/42] target/arm: Add is_secure parameter to regime_translation_disabled, Richard Henderson, 2022/10/01
[PATCH v3 05/42] target/arm: Split out get_phys_addr_with_secure, Richard Henderson, 2022/10/01
[PATCH v3 06/42] target/arm: Add is_secure parameter to v7m_read_half_insn, Richard Henderson, 2022/10/01
[PATCH v3 07/42] target/arm: Add TBFLAG_M32.SECURE, Richard Henderson, 2022/10/01
[PATCH v3 08/42] target/arm: Merge regime_is_secure into get_phys_addr, Richard Henderson, 2022/10/01
[PATCH v3 13/42] target/arm: Introduce arm_hcr_el2_eff_secstate, Richard Henderson, 2022/10/01
[PATCH v3 10/42] target/arm: Fold secure and non-secure a-profile mmu indexes, Richard Henderson, 2022/10/01
[PATCH v3 16/42] target/arm: Pass HCR to attribute subroutines., Richard Henderson, 2022/10/01