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[PULL 50/61] target/arm: Remove fpexc32_access
From: |
Peter Maydell |
Subject: |
[PULL 50/61] target/arm: Remove fpexc32_access |
Date: |
Fri, 22 Apr 2022 11:04:21 +0100 |
From: Richard Henderson <richard.henderson@linaro.org>
This function is incorrect in that it does not properly consider
CPTR_EL2.FPEN. We've already got another mechanism for raising
an FPU access trap: ARM_CP_FPU, so use that instead.
Remove CP_ACCESS_TRAP_FP_EL{2,3}, which becomes unused.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpu.h | 5 -----
target/arm/helper.c | 17 ++---------------
target/arm/op_helper.c | 13 -------------
3 files changed, 2 insertions(+), 33 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index d2a34f6ea8a..db8ff044497 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -2807,11 +2807,6 @@ typedef enum CPAccessResult {
/* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */
CP_ACCESS_TRAP_UNCATEGORIZED_EL2 = 5,
CP_ACCESS_TRAP_UNCATEGORIZED_EL3 = 6,
- /* Access fails and results in an exception syndrome for an FP access,
- * trapped directly to EL2 or EL3
- */
- CP_ACCESS_TRAP_FP_EL2 = 7,
- CP_ACCESS_TRAP_FP_EL3 = 8,
} CPAccessResult;
/* Access functions for coprocessor registers. These cannot fail and
diff --git a/target/arm/helper.c b/target/arm/helper.c
index f1e91b197e2..63397bbac1d 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -4784,18 +4784,6 @@ static void sctlr_write(CPUARMState *env, const
ARMCPRegInfo *ri,
}
}
-static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
- bool isread)
-{
- if ((env->cp15.cptr_el[2] & CPTR_TFP) && arm_current_el(env) == 2) {
- return CP_ACCESS_TRAP_FP_EL2;
- }
- if (env->cp15.cptr_el[3] & CPTR_TFP) {
- return CP_ACCESS_TRAP_FP_EL3;
- }
- return CP_ACCESS_OK;
-}
-
static void sdcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
@@ -5097,9 +5085,8 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
.access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
{ .name = "FPEXC32_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 5, .crm = 3, .opc2 = 0,
- .type = ARM_CP_ALIAS,
- .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]),
- .access = PL2_RW, .accessfn = fpexc32_access },
+ .access = PL2_RW, .type = ARM_CP_ALIAS | ARM_CP_FPU,
+ .fieldoffset = offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) },
{ .name = "DACR32_EL2", .state = ARM_CP_STATE_AA64,
.opc0 = 3, .opc1 = 4, .crn = 3, .crm = 0, .opc2 = 0,
.access = PL2_RW, .resetvalue = 0,
diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c
index 70b42b55fd0..2b87e8808b6 100644
--- a/target/arm/op_helper.c
+++ b/target/arm/op_helper.c
@@ -691,19 +691,6 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, void
*rip, uint32_t syndrome,
target_el = 3;
syndrome = syn_uncategorized();
break;
- case CP_ACCESS_TRAP_FP_EL2:
- target_el = 2;
- /* Since we are an implementation that takes exceptions on a trapped
- * conditional insn only if the insn has passed its condition code
- * check, we take the IMPDEF choice to always report CV=1 COND=0xe
- * (which is also the required value for AArch64 traps).
- */
- syndrome = syn_fp_access_trap(1, 0xe, false);
- break;
- case CP_ACCESS_TRAP_FP_EL3:
- target_el = 3;
- syndrome = syn_fp_access_trap(1, 0xe, false);
- break;
default:
g_assert_not_reached();
}
--
2.25.1
- [PULL 37/61] hw/intc/arm_gicv3: Update ID and feature registers for GICv4, (continued)
- [PULL 37/61] hw/intc/arm_gicv3: Update ID and feature registers for GICv4, Peter Maydell, 2022/04/22
- [PULL 30/61] hw/intc/arm_gicv3_redist: Factor out "update bit in pending table" code, Peter Maydell, 2022/04/22
- [PULL 33/61] hw/intc/arm_gicv3_redist: Use set_pending_table_bit() in mov handling, Peter Maydell, 2022/04/22
- [PULL 40/61] hw/arm/virt: Abstract out calculation of redistributor region capacity, Peter Maydell, 2022/04/22
- [PULL 45/61] target/arm: Change DisasContext.aarch64 to bool, Peter Maydell, 2022/04/22
- [PULL 43/61] target/arm: Update SCR_EL3 bits to ARMv8.8, Peter Maydell, 2022/04/22
- [PULL 44/61] target/arm: Update SCTLR bits to ARMv9.2, Peter Maydell, 2022/04/22
- [PULL 46/61] target/arm: Change CPUArchState.aarch64 to bool, Peter Maydell, 2022/04/22
- [PULL 47/61] target/arm: Extend store_cpu_offset to take field size, Peter Maydell, 2022/04/22
- [PULL 49/61] target/arm: Change CPUArchState.thumb to bool, Peter Maydell, 2022/04/22
- [PULL 50/61] target/arm: Remove fpexc32_access,
Peter Maydell <=
- [PULL 51/61] target/arm: Split out set_btype_raw, Peter Maydell, 2022/04/22
- [PULL 53/61] target/arm: Simplify GEN_SHIFT in translate.c, Peter Maydell, 2022/04/22
- [PULL 55/61] target/arm: Simplify aa32 DISAS_WFI, Peter Maydell, 2022/04/22
- [PULL 52/61] target/arm: Split out gen_rebuild_hflags, Peter Maydell, 2022/04/22
- [PULL 48/61] target/arm: Change DisasContext.thumb to bool, Peter Maydell, 2022/04/22
- [PULL 54/61] target/arm: Simplify gen_sar, Peter Maydell, 2022/04/22
- [PULL 56/61] target/arm: Use tcg_constant in translate-m-nocp.c, Peter Maydell, 2022/04/22
- [PULL 57/61] target/arm: Use tcg_constant in translate-neon.c, Peter Maydell, 2022/04/22
- [PULL 61/61] hw/arm/smmuv3: Pass the actual perm to returned IOMMUTLBEntry in smmuv3_translate(), Peter Maydell, 2022/04/22
- [PULL 58/61] target/arm: Use smin/smax for do_sat_addsub_32, Peter Maydell, 2022/04/22