[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[PULL 10/41] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v
From: |
Philippe Mathieu-Daudé |
Subject: |
[PULL 10/41] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v |
Date: |
Tue, 2 Nov 2021 14:42:09 +0100 |
This 'shift amount' format is not always 16-bit, so name it
generically as 'sa'. This will help to unify the various
arg_msa decodetree generated structures.
Rename the @bz format -> @bz_v (specific @bz with df=3) and
@bz_df -> @bz (generic @bz).
Since we modify &msa_bz, re-align its arguments, so the other
structures added in the following commits stay visually aligned.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20211028210843.2120802-8-f4bug@amsat.org>
---
target/mips/tcg/msa.decode | 15 +++++++--------
target/mips/tcg/msa_translate.c | 20 ++++++++++----------
2 files changed, 17 insertions(+), 18 deletions(-)
diff --git a/target/mips/tcg/msa.decode b/target/mips/tcg/msa.decode
index 74d99f6862c..56419a24eb9 100644
--- a/target/mips/tcg/msa.decode
+++ b/target/mips/tcg/msa.decode
@@ -13,19 +13,18 @@
&r rs rt rd sa
-&msa_bz df wt s16
+&msa_bz df wt sa
@lsa ...... rs:5 rt:5 rd:5 ... sa:2 ...... &r
-@bz ...... ... .. wt:5 s16:16 &msa_bz df=3
-@bz_df ...... ... df:2 wt:5 s16:16 &msa_bz
+@bz_v ...... ... .. wt:5 sa:16 &msa_bz df=3
+@bz ...... ... df:2 wt:5 sa:16 &msa_bz
LSA 000000 ..... ..... ..... 000 .. 000101 @lsa
DLSA 000000 ..... ..... ..... 000 .. 010101 @lsa
-BZ_V 010001 01011 ..... ................ @bz
-BNZ_V 010001 01111 ..... ................ @bz
-
-BZ_x 010001 110 .. ..... ................ @bz_df
-BNZ_x 010001 111 .. ..... ................ @bz_df
+BZ_V 010001 01011 ..... ................ @bz_v
+BNZ_V 010001 01111 ..... ................ @bz_v
+BZ 010001 110 .. ..... ................ @bz
+BNZ 010001 111 .. ..... ................ @bz
MSA 011110 --------------------------
diff --git a/target/mips/tcg/msa_translate.c b/target/mips/tcg/msa_translate.c
index 56a0148fec2..8311730f0a5 100644
--- a/target/mips/tcg/msa_translate.c
+++ b/target/mips/tcg/msa_translate.c
@@ -340,7 +340,7 @@ static void gen_check_zero_element(TCGv tresult, uint8_t
df, uint8_t wt,
tcg_temp_free_i64(t1);
}
-static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int s16, TCGCond cond)
+static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int sa, TCGCond cond)
{
TCGv_i64 t0;
@@ -358,7 +358,7 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int
s16, TCGCond cond)
tcg_gen_trunc_i64_tl(bcond, t0);
tcg_temp_free_i64(t0);
- ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+ ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
ctx->hflags |= MIPS_HFLAG_BC;
ctx->hflags |= MIPS_HFLAG_BDS32;
@@ -368,15 +368,15 @@ static bool gen_msa_BxZ_V(DisasContext *ctx, int wt, int
s16, TCGCond cond)
static bool trans_BZ_V(DisasContext *ctx, arg_msa_bz *a)
{
- return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_EQ);
+ return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_EQ);
}
static bool trans_BNZ_V(DisasContext *ctx, arg_msa_bz *a)
{
- return gen_msa_BxZ_V(ctx, a->wt, a->s16, TCG_COND_NE);
+ return gen_msa_BxZ_V(ctx, a->wt, a->sa, TCG_COND_NE);
}
-static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int s16, bool
if_not)
+static bool gen_msa_BxZ(DisasContext *ctx, int df, int wt, int sa, bool if_not)
{
if (!check_msa_enabled(ctx)) {
return true;
@@ -389,21 +389,21 @@ static bool gen_msa_BxZ(DisasContext *ctx, int df, int
wt, int s16, bool if_not)
gen_check_zero_element(bcond, df, wt, if_not ? TCG_COND_EQ : TCG_COND_NE);
- ctx->btarget = ctx->base.pc_next + (s16 << 2) + 4;
+ ctx->btarget = ctx->base.pc_next + (sa << 2) + 4;
ctx->hflags |= MIPS_HFLAG_BC;
ctx->hflags |= MIPS_HFLAG_BDS32;
return true;
}
-static bool trans_BZ_x(DisasContext *ctx, arg_msa_bz *a)
+static bool trans_BZ(DisasContext *ctx, arg_msa_bz *a)
{
- return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, false);
+ return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, false);
}
-static bool trans_BNZ_x(DisasContext *ctx, arg_msa_bz *a)
+static bool trans_BNZ(DisasContext *ctx, arg_msa_bz *a)
{
- return gen_msa_BxZ(ctx, a->df, a->wt, a->s16, true);
+ return gen_msa_BxZ(ctx, a->df, a->wt, a->sa, true);
}
static void gen_msa_i8(DisasContext *ctx)
--
2.31.1
- [PULL 00/41] MIPS patches for 2021-11-02, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 01/41] MAINTAINERS: Add MIPS general architecture support entry, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 02/41] MAINTAINERS: Add entries to cover MIPS CPS / GIC hardware, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 03/41] MAINTAINERS: Split MIPS TCG frontend vs MIPS machines/hardware, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 04/41] target/mips: Fix MSA MADDV.B opcode, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 05/41] target/mips: Fix MSA MSUBV.B opcode, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 06/41] target/mips: Adjust style in msa_translate_init(), Philippe Mathieu-Daudé, 2021/11/02
- [PULL 07/41] target/mips: Use dup_const() to simplify, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 08/41] target/mips: Have check_msa_access() return a boolean, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 09/41] target/mips: Use enum definitions from CPUMIPSMSADataFormat enum, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 10/41] target/mips: Rename sa16 -> sa, bz_df -> bz -> bz_v,
Philippe Mathieu-Daudé <=
- [PULL 11/41] target/mips: Convert MSA LDI opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 12/41] target/mips: Convert MSA I5 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 13/41] target/mips: Convert MSA BIT instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 14/41] target/mips: Convert MSA SHF opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 15/41] target/mips: Convert MSA I8 instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 16/41] target/mips: Convert MSA load/store instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 17/41] target/mips: Convert MSA 2RF instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 18/41] target/mips: Convert MSA FILL opcode to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 19/41] target/mips: Convert MSA 2R instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02
- [PULL 20/41] target/mips: Convert MSA VEC instruction format to decodetree, Philippe Mathieu-Daudé, 2021/11/02