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[Qemu-devel] [PATCH 2/3] target/mips: Add emulation of MMI instruction P
From: |
Mateja Marjanovic |
Subject: |
[Qemu-devel] [PATCH 2/3] target/mips: Add emulation of MMI instruction PCPYLD |
Date: |
Mon, 25 Feb 2019 17:10:36 +0100 |
Add emulation of MMI instruction PCPYLD. The emulation is implemented
using TCG front end operations directly to achieve better performance.
Signed-off-by: Mateja Marjanovic <address@hidden>
---
target/mips/translate.c | 42 +++++++++++++++++++++++++++++++++++++++++-
1 file changed, 41 insertions(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index a3a5f9b..117a29c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24416,6 +24416,44 @@ static void gen_mmi_pcpyh(DisasContext *ctx)
}
}
+/*
+ * PCPYLD rd, rs, rt
+ *
+ * Parallel Copy Lower Doubleword
+ *
+ * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
+ * +-----------+---------+---------+---------+---------+-----------+
+ * | MMI | rs | rt | rd | PCPYLD | MMI2 |
+ * +-----------+---------+---------+---------+---------+-----------+
+ */
+static void gen_mmi_pcpyld(DisasContext *ctx)
+{
+ uint32_t rs, rt, rd;
+ uint32_t opcode;
+
+ opcode = ctx->opcode;
+
+ rs = extract32(opcode, 21, 5);
+ rt = extract32(opcode, 16, 5);
+ rd = extract32(opcode, 11, 5);
+
+ if (rd == 0) {
+ /* nop */
+ } else if ((rt == 0) && (rs == 0)) {
+ tcg_gen_movi_i64(cpu_gpr[rt], 0);
+ tcg_gen_movi_i64(cpu_mmr[rt], 0);
+ } else if (rt == 0) {
+ tcg_gen_movi_i64(cpu_gpr[rd], 0);
+ tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]);
+ } else if (rs == 0) {
+ tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]);
+ tcg_gen_movi_i64(cpu_mmr[rd], 0);
+ } else {
+ tcg_gen_mov_i64(cpu_gpr[rd], cpu_gpr[rt]);
+ tcg_gen_mov_i64(cpu_mmr[rd], cpu_gpr[rs]);
+ }
+}
+
#endif
@@ -27430,7 +27468,6 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext
*ctx)
case MMI_OPC_2_PINTH: /* TODO: MMI_OPC_2_PINTH */
case MMI_OPC_2_PMULTW: /* TODO: MMI_OPC_2_PMULTW */
case MMI_OPC_2_PDIVW: /* TODO: MMI_OPC_2_PDIVW */
- case MMI_OPC_2_PCPYLD: /* TODO: MMI_OPC_2_PCPYLD */
case MMI_OPC_2_PMADDH: /* TODO: MMI_OPC_2_PMADDH */
case MMI_OPC_2_PHMADH: /* TODO: MMI_OPC_2_PHMADH */
case MMI_OPC_2_PAND: /* TODO: MMI_OPC_2_PAND */
@@ -27445,6 +27482,9 @@ static void decode_mmi2(CPUMIPSState *env, DisasContext
*ctx)
case MMI_OPC_2_PROT3W: /* TODO: MMI_OPC_2_PROT3W */
generate_exception_end(ctx, EXCP_RI); /* TODO: MMI_OPC_CLASS_MMI2 */
break;
+ case MMI_OPC_2_PCPYLD:
+ gen_mmi_pcpyld(ctx);
+ break;
default:
MIPS_INVAL("TX79 MMI class MMI2");
generate_exception_end(ctx, EXCP_RI);
--
2.7.4