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[Qemu-devel] [PATCH v7 30/35] target/riscv: Remove decode_RV32_64G()
From: |
Palmer Dabbelt |
Subject: |
[Qemu-devel] [PATCH v7 30/35] target/riscv: Remove decode_RV32_64G() |
Date: |
Wed, 13 Feb 2019 07:54:09 -0800 |
From: Bastian Koppelmann <address@hidden>
decodetree handles all instructions now so the fallback is not necessary
anymore.
Reviewed-by: Richard Henderson <address@hidden>
Signed-off-by: Bastian Koppelmann <address@hidden>
Signed-off-by: Peer Adelt <address@hidden>
---
target/riscv/translate.c | 21 +--------------------
1 file changed, 1 insertion(+), 20 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 65bedc966497..59c297915158 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -646,24 +646,6 @@ bool decode_insn16(DisasContext *ctx, uint16_t insn);
#include "decode_insn16.inc.c"
#include "insn_trans/trans_rvc.inc.c"
-static void decode_RV32_64G(DisasContext *ctx)
-{
- uint32_t op;
-
- /* We do not do misaligned address check here: the address should never be
- * misaligned at this point. Instructions that set PC must do the check,
- * since epc must be the address of the instruction that caused us to
- * perform the misaligned instruction fetch */
-
- op = MASK_OP_MAJOR(ctx->opcode);
-
- switch (op) {
- default:
- gen_exception_illegal(ctx);
- break;
- }
-}
-
static void decode_opc(DisasContext *ctx)
{
/* check for compressed insn */
@@ -680,8 +662,7 @@ static void decode_opc(DisasContext *ctx)
} else {
ctx->pc_succ_insn = ctx->base.pc_next + 4;
if (!decode_insn32(ctx, ctx->opcode)) {
- /* fallback to old decoder */
- decode_RV32_64G(ctx);
+ gen_exception_illegal(ctx);
}
}
}
--
2.18.1
- [Qemu-devel] [PATCH v7 00/35] target/riscv: Convert to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 03/35] target/riscv: Convert RVXI branch insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 08/35] target/riscv: Convert RVXI csr insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 02/35] target/riscv: Activate decodetree and implemnt LUI & AUIPC, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 07/35] target/riscv: Convert RVXI fence insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 09/35] target/riscv: Convert RVXM insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 10/35] target/riscv: Convert RV32A insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 34/35] target/riscv: Splice remaining compressed insn pairs for riscv32 vs riscv64, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 28/35] target/riscv: Rename trans_arith to gen_arith, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 30/35] target/riscv: Remove decode_RV32_64G(),
Palmer Dabbelt <=
- [Qemu-devel] [PATCH v7 21/35] target/riscv: Remove manual decoding from gen_branch(), Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 13/35] target/riscv: Convert RV64F insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 35/35] target/riscv: Remaining rvc insn reuse 32 bit translators, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 05/35] target/riscv: Convert RV64I load/store insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 01/35] target/riscv: Move CPURISCVState pointer to DisasContext, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 24/35] target/riscv: Move gen_arith_imm() decoding into trans_* functions, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 04/35] target/riscv: Convert RV32I load/store insns to decodetree, Palmer Dabbelt, 2019/02/13
- [Qemu-devel] [PATCH v7 23/35] target/riscv: Remove manual decoding from gen_store(), Palmer Dabbelt, 2019/02/13