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[Qemu-devel] [PULL 11/47] hw/arm/armsse: Make SRAM bank size configurabl
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 11/47] hw/arm/armsse: Make SRAM bank size configurable |
Date: |
Fri, 1 Feb 2019 16:06:17 +0000 |
For the IoTKit the SRAM bank size is always 32K (15 bits); for the
SSE-200 this is a configurable parameter, which defaults to 32K but
can be changed when it is built into a particular SoC. For instance
the Musca-B1 board sets it to 128K (17 bits).
Make the bank size a QOM property. We follow the SSE-200 hardware in
naming the parameter SRAM_ADDR_WIDTH, which specifies the number of
address bits of a single SRAM bank.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
include/hw/arm/armsse.h | 1 +
hw/arm/armsse.c | 18 ++++++++++++++++--
2 files changed, 17 insertions(+), 2 deletions(-)
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index 99714aa63cd..e4a05013316 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -146,6 +146,7 @@ typedef struct ARMSSE {
MemoryRegion *board_memory;
uint32_t exp_numirq;
uint32_t mainclk_frq;
+ uint32_t sram_addr_width;
} ARMSSE;
typedef struct ARMSSEInfo ARMSSEInfo;
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index b639b54e0db..a2ae5d3c4b9 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -221,6 +221,7 @@ static void armsse_realize(DeviceState *dev, Error **errp)
DeviceState *dev_apb_ppc1;
DeviceState *dev_secctl;
DeviceState *dev_splitter;
+ uint32_t addr_width_max;
if (!s->board_memory) {
error_setg(errp, "memory property was not set");
@@ -232,6 +233,15 @@ static void armsse_realize(DeviceState *dev, Error **errp)
return;
}
+ /* max SRAM_ADDR_WIDTH: 24 - log2(SRAM_NUM_BANK) */
+ assert(is_power_of_2(info->sram_banks));
+ addr_width_max = 24 - ctz32(info->sram_banks);
+ if (s->sram_addr_width < 1 || s->sram_addr_width > addr_width_max) {
+ error_setg(errp, "SRAM_ADDR_WIDTH must be between 1 and %d",
+ addr_width_max);
+ return;
+ }
+
/* Handling of which devices should be available only to secure
* code is usually done differently for M profile than for A profile.
* Instead of putting some devices only into the secure address space,
@@ -352,8 +362,10 @@ static void armsse_realize(DeviceState *dev, Error **errp)
for (i = 0; i < info->sram_banks; i++) {
char *ramname = g_strdup_printf("armsse.sram%d", i);
SysBusDevice *sbd_mpc;
+ uint32_t sram_bank_size = 1 << s->sram_addr_width;
- memory_region_init_ram(&s->sram[i], NULL, ramname, 0x00008000, &err);
+ memory_region_init_ram(&s->sram[i], NULL, ramname,
+ sram_bank_size, &err);
g_free(ramname);
if (err) {
error_propagate(errp, err);
@@ -372,7 +384,8 @@ static void armsse_realize(DeviceState *dev, Error **errp)
}
/* Map the upstream end of the MPC into the right place... */
sbd_mpc = SYS_BUS_DEVICE(&s->mpc[i]);
- memory_region_add_subregion(&s->container, 0x20000000 + i * 0x8000,
+ memory_region_add_subregion(&s->container,
+ 0x20000000 + i * sram_bank_size,
sysbus_mmio_get_region(sbd_mpc, 1));
/* ...and its register interface */
memory_region_add_subregion(&s->container, 0x50083000 + i * 0x1000,
@@ -748,6 +761,7 @@ static Property armsse_properties[] = {
MemoryRegion *),
DEFINE_PROP_UINT32("EXP_NUMIRQ", ARMSSE, exp_numirq, 64),
DEFINE_PROP_UINT32("MAINCLK", ARMSSE, mainclk_frq, 0),
+ DEFINE_PROP_UINT32("SRAM_ADDR_WIDTH", ARMSSE, sram_addr_width, 15),
DEFINE_PROP_END_OF_LIST()
};
--
2.20.1
- [Qemu-devel] [PULL 16/47] hw/arm/armsse: Add unimplemented-device stubs for MHUs, (continued)
- [Qemu-devel] [PULL 16/47] hw/arm/armsse: Add unimplemented-device stubs for MHUs, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 39/47] target/arm: Always enable pac keys for user-only, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 09/47] hw/misc/iotkit-secctl: Support 4 internal MPCs, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 24/47] hw/arm/mps2-tz: Add mps2-an521 model, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 43/47] target/arm: fix AArch64 virtual address space size, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 44/47] target/arm: fix decoding of B{, L}RA{A, B}, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 26/47] target/arm/translate-a64: Don't underdecode PRFM, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 11/47] hw/arm/armsse: Make SRAM bank size configurable,
Peter Maydell <=
- [Qemu-devel] [PULL 20/47] hw/misc/armsse-cpuid: Implement SSE-200 CPU_IDENTITY register block, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 47/47] tests/microbit-test: Add tests for nRF51 NVMC, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 36/47] target/arm: Add a timer to predict PMU counter overflow, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 12/47] hw/arm/armsse: Support dual-CPU configuration, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 38/47] arm: Clarify the logic of set_pc(), Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 45/47] hw/nvram/nrf51_nvm: Add nRF51 non-volatile memories, Peter Maydell, 2019/02/01
- Re: [Qemu-devel] [PULL 00/47] target-arm queue, Peter Maydell, 2019/02/01
- Re: [Qemu-devel] [PULL 00/47] target-arm queue, no-reply, 2019/02/03