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[Qemu-devel] [PULL 22/47] hw/arm/armsse: Add SSE-200 model
From: |
Peter Maydell |
Subject: |
[Qemu-devel] [PULL 22/47] hw/arm/armsse: Add SSE-200 model |
Date: |
Fri, 1 Feb 2019 16:06:28 +0000 |
Add a model of the SSE-200, now we have put in all
the code that lets us make it different from the IoTKit.
Signed-off-by: Peter Maydell <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-id: address@hidden
---
include/hw/arm/armsse.h | 19 ++++++++++++++++---
hw/arm/armsse.c | 12 ++++++++++++
2 files changed, 28 insertions(+), 3 deletions(-)
diff --git a/include/hw/arm/armsse.h b/include/hw/arm/armsse.h
index 3914e8e4bf2..f800bafb14a 100644
--- a/include/hw/arm/armsse.h
+++ b/include/hw/arm/armsse.h
@@ -1,5 +1,5 @@
/*
- * ARM SSE (Subsystems for Embedded): IoTKit
+ * ARM SSE (Subsystems for Embedded): IoTKit, SSE-200
*
* Copyright (c) 2018 Linaro Limited
* Written by Peter Maydell
@@ -12,9 +12,13 @@
/*
* This is a model of the Arm "Subsystems for Embedded" family of
* hardware, which include the IoT Kit and the SSE-050, SSE-100 and
- * SSE-200. Currently we model only the Arm IoT Kit which is documented in
+ * SSE-200. Currently we model:
+ * - the Arm IoT Kit which is documented in
*
http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ecm0601256/index.html
- * It contains:
+ * - the SSE-200 which is documented in
+ *
http://infocenter.arm.com/help/topic/com.arm.doc.101104_0100_00_en/corelink_sse200_subsystem_for_embedded_technical_reference_manual_101104_0100_00_en.pdf
+ *
+ * The IoTKit contains:
* a Cortex-M33
* the IDAU
* some timers and watchdogs
@@ -23,6 +27,14 @@
* a security controller
* a bus fabric which arranges that some parts of the address
* space are secure and non-secure aliases of each other
+ * The SSE-200 additionally contains:
+ * a second Cortex-M33
+ * two Message Handling Units (MHUs)
+ * an optional CryptoCell (which we do not model)
+ * more SRAM banks with associated MPCs
+ * multiple Power Policy Units (PPUs)
+ * a control interface for an icache for each CPU
+ * per-CPU identity and control register blocks
*
* QEMU interface:
* + QOM property "memory" is a MemoryRegion containing the devices provided
@@ -93,6 +105,7 @@
* them via the ARMSSE base class, so they have no IOTKIT() etc macros.
*/
#define TYPE_IOTKIT "iotkit"
+#define TYPE_SSE200 "sse-200"
/* We have an IRQ splitter and an OR gate input for each external PPC
* and the 2 internal PPCs
diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c
index eb691faf720..5d53071a5a0 100644
--- a/hw/arm/armsse.c
+++ b/hw/arm/armsse.c
@@ -50,6 +50,18 @@ static const ARMSSEInfo armsse_variants[] = {
.has_cpusecctrl = false,
.has_cpuid = false,
},
+ {
+ .name = TYPE_SSE200,
+ .sram_banks = 4,
+ .num_cpus = 2,
+ .sys_version = 0x22041743,
+ .sys_config_format = SSE200Format,
+ .has_mhus = true,
+ .has_ppus = true,
+ .has_cachectrl = true,
+ .has_cpusecctrl = true,
+ .has_cpuid = true,
+ },
};
static uint32_t armsse_sys_config_value(ARMSSE *s, const ARMSSEInfo *info)
--
2.20.1
- [Qemu-devel] [PULL 00/47] target-arm queue, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 02/47] armv7m: Don't assume the NVIC's CPU is CPU 0, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 01/47] hw/arm/nrf51_soc: set object owner in memory_region_init_ram, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 03/47] armv7m: Make cpu object a child of the armv7m container, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 04/47] armv7m: Pass through start-powered-off CPU property, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 18/47] hw/arm/armsse: Add unimplemented-device stub for cache control registers, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 05/47] hw/arm/iotkit: Rename IoTKit to ARMSSE, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 14/47] hw/arm/armsse: Put each CPU in its own cluster object, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 06/47] hw/arm/iotkit: Refactor into abstract base class and subclass, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 29/47] target/arm/translate-a64: Don't underdecode add/sub extended register, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 22/47] hw/arm/armsse: Add SSE-200 model,
Peter Maydell <=
- [Qemu-devel] [PULL 07/47] hw/arm/iotkit: Rename 'iotkit' local variables and functions, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 21/47] hw/arm/armsse: Add CPU_IDENTITY block to SSE-200, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 42/47] linux-user: Initialize aarch64 pac keys, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 31/47] target/arm/translate-a64: Don't underdecode SDOT and UDOT, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 27/47] target/arm/translate-a64: Don't underdecode SIMD ld/st multiple, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 35/47] target/arm: Send interrupts on PMU counter overflow, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 25/47] target/arm/translate-a64: Don't underdecode system instructions, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 40/47] aarch64-linux-user: Update HWCAP bits from linux 5.0-rc1, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 30/47] target/arm/translate-a64: Don't underdecode FP insns, Peter Maydell, 2019/02/01
- [Qemu-devel] [PULL 13/47] hw/arm/armsse: Give each CPU its own view of memory, Peter Maydell, 2019/02/01