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[Qemu-devel] [PULL 21/42] tcg: Add RISC-V cpu signal handler
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PULL 21/42] tcg: Add RISC-V cpu signal handler |
Date: |
Wed, 26 Dec 2018 07:55:08 +1100 |
From: Alistair Francis <address@hidden>
Signed-off-by: Alistair Francis <address@hidden>
Signed-off-by: Michael Clark <address@hidden>
Reviewed-by: Richard Henderson <address@hidden>
Message-Id: <address@hidden>
Signed-off-by: Richard Henderson <address@hidden>
---
accel/tcg/user-exec.c | 75 +++++++++++++++++++++++++++++++++++++++++++
1 file changed, 75 insertions(+)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index cd75829cf2..941295ea49 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -571,6 +571,81 @@ int cpu_signal_handler(int host_signum, void *pinfo,
return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
}
+#elif defined(__riscv)
+
+int cpu_signal_handler(int host_signum, void *pinfo,
+ void *puc)
+{
+ siginfo_t *info = pinfo;
+ ucontext_t *uc = puc;
+ greg_t pc = uc->uc_mcontext.__gregs[REG_PC];
+ uint32_t insn = *(uint32_t *)pc;
+ int is_write = 0;
+
+ /* Detect store by reading the instruction at the program
+ counter. Note: we currently only generate 32-bit
+ instructions so we thus only detect 32-bit stores */
+ switch (((insn >> 0) & 0b11)) {
+ case 3:
+ switch (((insn >> 2) & 0b11111)) {
+ case 8:
+ switch (((insn >> 12) & 0b111)) {
+ case 0: /* sb */
+ case 1: /* sh */
+ case 2: /* sw */
+ case 3: /* sd */
+ case 4: /* sq */
+ is_write = 1;
+ break;
+ default:
+ break;
+ }
+ break;
+ case 9:
+ switch (((insn >> 12) & 0b111)) {
+ case 2: /* fsw */
+ case 3: /* fsd */
+ case 4: /* fsq */
+ is_write = 1;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+ }
+
+ /* Check for compressed instructions */
+ switch (((insn >> 13) & 0b111)) {
+ case 7:
+ switch (insn & 0b11) {
+ case 0: /*c.sd */
+ case 2: /* c.sdsp */
+ is_write = 1;
+ break;
+ default:
+ break;
+ }
+ break;
+ case 6:
+ switch (insn & 0b11) {
+ case 0: /* c.sw */
+ case 3: /* c.swsp */
+ is_write = 1;
+ break;
+ default:
+ break;
+ }
+ break;
+ default:
+ break;
+ }
+
+ return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask);
+}
+
#else
#error host CPU specific signal handler needed
--
2.17.2
- [Qemu-devel] [PULL 11/42] tcg/riscv: Add the mov and movi instruction, (continued)
- [Qemu-devel] [PULL 11/42] tcg/riscv: Add the mov and movi instruction, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 12/42] tcg/riscv: Add the extract instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 14/42] tcg/riscv: Add the add2 and sub2 instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 13/42] tcg/riscv: Add the out load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 15/42] tcg/riscv: Add branch and jump instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 16/42] tcg/riscv: Add slowpath load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 17/42] tcg/riscv: Add direct load and store instructions, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 18/42] tcg/riscv: Add the out op decoder, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 19/42] tcg/riscv: Add the prologue generation and register the JIT, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 20/42] tcg/riscv: Add the target init code, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 21/42] tcg: Add RISC-V cpu signal handler,
Richard Henderson <=
- [Qemu-devel] [PULL 22/42] disas: Add RISC-V support, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 23/42] configure: Add support for building RISC-V host, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 24/42] disas/microblaze: Remove unused REG_SP macro, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 25/42] linux-user: Add safe_syscall for riscv64 host, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 26/42] tcg: Renumber TCG_CALL_* flags, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 27/42] tcg: Add TCG_CALL_NO_RETURN, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 28/42] tcg: Reference count labels, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 29/42] tcg: Add reachable_code_pass, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 30/42] tcg: Add preferred_reg argument to tcg_reg_alloc, Richard Henderson, 2018/12/25
- [Qemu-devel] [PULL 31/42] tcg: Add preferred_reg argument to temp_load, Richard Henderson, 2018/12/25