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Re: [Qemu-devel] [PATCH 07/15] spapr_pci: Define SPAPR_MAX_PHBS in hw/pc
From: |
Cédric Le Goater |
Subject: |
Re: [Qemu-devel] [PATCH 07/15] spapr_pci: Define SPAPR_MAX_PHBS in hw/pci-host/spapr.h |
Date: |
Fri, 21 Dec 2018 09:03:49 +0100 |
User-agent: |
Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.3.1 |
On 12/21/18 1:36 AM, Greg Kurz wrote:
> PHB hotplug will bring more users for it. Let's define it along with
> the PHB defines from which it is derived for simplicity.
>
> While here fix a misleading comment about manual placement, which was
> abandoned with 30b3bc5aa9f4.
>
> Signed-off-by: Greg Kurz <address@hidden>
Reviewed-by: Cédric Le Goater <address@hidden>
> ---
> hw/ppc/spapr.c | 2 --
> include/hw/pci-host/spapr.h | 6 ++++--
> 2 files changed, 4 insertions(+), 4 deletions(-)
>
> diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
> index 621006eaa862..fe3f9829ae6c 100644
> --- a/hw/ppc/spapr.c
> +++ b/hw/ppc/spapr.c
> @@ -3838,8 +3838,6 @@ static void spapr_phb_placement(sPAPRMachineState
> *spapr, uint32_t index,
> * 1TiB 64-bit MMIO windows for each PHB.
> */
> const uint64_t base_buid = 0x800000020000000ULL;
> -#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
> - SPAPR_PCI_MEM64_WIN_SIZE - 1)
> int i;
>
> /* Sanity check natural alignments */
> diff --git a/include/hw/pci-host/spapr.h b/include/hw/pci-host/spapr.h
> index 9d2ec1a410e8..83d5075a6ef3 100644
> --- a/include/hw/pci-host/spapr.h
> +++ b/include/hw/pci-host/spapr.h
> @@ -94,11 +94,13 @@ struct sPAPRPHBState {
> ((1ULL << 32) - SPAPR_PCI_MEM_WIN_BUS_OFFSET)
> #define SPAPR_PCI_MEM64_WIN_SIZE 0x10000000000ULL /* 1 TiB */
>
> -/* Without manual configuration, all PCI outbound windows will be
> - * within this range */
> +/* All PCI outbound windows will be within this range */
> #define SPAPR_PCI_BASE (1ULL << 45) /* 32 TiB */
> #define SPAPR_PCI_LIMIT (1ULL << 46) /* 64 TiB */
>
> +#define SPAPR_MAX_PHBS ((SPAPR_PCI_LIMIT - SPAPR_PCI_BASE) / \
> + SPAPR_PCI_MEM64_WIN_SIZE - 1)
> +
Which is 32. Good, this is in sync with the IRQ number ranges.
C.
> #define SPAPR_PCI_2_7_MMIO_WIN_SIZE 0xf80000000
> #define SPAPR_PCI_IO_WIN_SIZE 0x10000
>
>
- [Qemu-devel] [PATCH 00/15] spapr: Add support for PHB hotplug, Greg Kurz, 2018/12/20
- [Qemu-devel] [PATCH 01/15] ppc/spapr: Receive and store device tree blob from SLOF, Greg Kurz, 2018/12/20
- [Qemu-devel] [PATCH 02/15] spapr: move spapr_create_phb() to core machine code, Greg Kurz, 2018/12/20
- [Qemu-devel] [PATCH 03/15] pci: allow cleanup/unregistration of PCI root buses, Greg Kurz, 2018/12/20
- [Qemu-devel] [PATCH 04/15] spapr_pci: add proper rollback on PHB realize error path, Greg Kurz, 2018/12/20
- [Qemu-devel] [PATCH 05/15] spapr_pci: add PHB unrealize, Greg Kurz, 2018/12/20
- [Qemu-devel] [PATCH 06/15] spapr: enable PHB hotplug for default pseries machine type, Greg Kurz, 2018/12/20
- [Qemu-devel] [PATCH 07/15] spapr_pci: Define SPAPR_MAX_PHBS in hw/pci-host/spapr.h, Greg Kurz, 2018/12/20
- Re: [Qemu-devel] [PATCH 07/15] spapr_pci: Define SPAPR_MAX_PHBS in hw/pci-host/spapr.h,
Cédric Le Goater <=
- [Qemu-devel] [PATCH 08/15] spapr: create DR connectors for PHBs, Greg Kurz, 2018/12/20
- [Qemu-devel] [PATCH 09/15] spapr: populate PHB DRC entries for root DT node, Greg Kurz, 2018/12/20
- [Qemu-devel] [PATCH 10/15] spapr_events: add support for phb hotplug events, Greg Kurz, 2018/12/20
- [Qemu-devel] [PATCH 11/15] qdev: pass an Object * to qbus_set_hotplug_handler(), Greg Kurz, 2018/12/20
- [Qemu-devel] [PATCH 12/15] spapr_pci: provide node start offset via spapr_populate_pci_dt(), Greg Kurz, 2018/12/20
- [Qemu-devel] [PATCH 13/15] spapr_pci: add ibm, my-drc-index property for PHB hotplug, Greg Kurz, 2018/12/20
- [Qemu-devel] [PATCH 14/15] spapr: Expose the name of the interrupt controller node, Greg Kurz, 2018/12/21