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[Qemu-devel] [PULL v3 12/44] qapi: Define PCIe link speed and width prop
From: |
Michael S. Tsirkin |
Subject: |
[Qemu-devel] [PULL v3 12/44] qapi: Define PCIe link speed and width properties |
Date: |
Thu, 20 Dec 2018 13:38:43 -0500 |
From: Alex Williamson <address@hidden>
Create properties to be able to define speeds and widths for PCIe
links. The only tricky bit here is that our get and set callbacks
translate from the fixed QAPI automagic enums to those we define
in PCI code to represent the actual register segment value.
Cc: Eric Blake <address@hidden>
Tested-by: Geoffrey McRae <address@hidden>
Reviewed-by: Markus Armbruster <address@hidden>
Signed-off-by: Alex Williamson <address@hidden>
Reviewed-by: Michael S. Tsirkin <address@hidden>
Signed-off-by: Michael S. Tsirkin <address@hidden>
---
qapi/common.json | 42 +++++++++
include/hw/qdev-properties.h | 8 ++
hw/core/qdev-properties.c | 176 +++++++++++++++++++++++++++++++++++
3 files changed, 226 insertions(+)
diff --git a/qapi/common.json b/qapi/common.json
index 021174f04e..99d313ef3b 100644
--- a/qapi/common.json
+++ b/qapi/common.json
@@ -127,6 +127,48 @@
{ 'enum': 'OffAutoPCIBAR',
'data': [ 'off', 'auto', 'bar0', 'bar1', 'bar2', 'bar3', 'bar4', 'bar5' ] }
+##
+# @PCIELinkSpeed:
+#
+# An enumeration of PCIe link speeds in units of GT/s
+#
+# @2_5: 2.5GT/s
+#
+# @5: 5.0GT/s
+#
+# @8: 8.0GT/s
+#
+# @16: 16.0GT/s
+#
+# Since: 4.0
+##
+{ 'enum': 'PCIELinkSpeed',
+ 'data': [ '2_5', '5', '8', '16' ] }
+
+##
+# @PCIELinkWidth:
+#
+# An enumeration of PCIe link width
+#
+# @1: x1
+#
+# @2: x2
+#
+# @4: x4
+#
+# @8: x8
+#
+# @12: x12
+#
+# @16: x16
+#
+# @32: x32
+#
+# Since: 4.0
+##
+{ 'enum': 'PCIELinkWidth',
+ 'data': [ '1', '2', '4', '8', '12', '16', '32' ] }
+
##
# @SysEmuTarget:
#
diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h
index 3ab9cd2eb6..b6758c852e 100644
--- a/include/hw/qdev-properties.h
+++ b/include/hw/qdev-properties.h
@@ -36,6 +36,8 @@ extern const PropertyInfo qdev_prop_uuid;
extern const PropertyInfo qdev_prop_arraylen;
extern const PropertyInfo qdev_prop_link;
extern const PropertyInfo qdev_prop_off_auto_pcibar;
+extern const PropertyInfo qdev_prop_pcie_link_speed;
+extern const PropertyInfo qdev_prop_pcie_link_width;
#define DEFINE_PROP(_name, _state, _field, _prop, _type) { \
.name = (_name), \
@@ -217,6 +219,12 @@ extern const PropertyInfo qdev_prop_off_auto_pcibar;
#define DEFINE_PROP_OFF_AUTO_PCIBAR(_n, _s, _f, _d) \
DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_off_auto_pcibar, \
OffAutoPCIBAR)
+#define DEFINE_PROP_PCIE_LINK_SPEED(_n, _s, _f, _d) \
+ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_pcie_link_speed, \
+ PCIExpLinkSpeed)
+#define DEFINE_PROP_PCIE_LINK_WIDTH(_n, _s, _f, _d) \
+ DEFINE_PROP_SIGNED(_n, _s, _f, _d, qdev_prop_pcie_link_width, \
+ PCIExpLinkWidth)
#define DEFINE_PROP_UUID(_name, _state, _field) { \
.name = (_name), \
diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c
index bd84c4ea4c..943dc2654b 100644
--- a/hw/core/qdev-properties.c
+++ b/hw/core/qdev-properties.c
@@ -1297,3 +1297,179 @@ const PropertyInfo qdev_prop_off_auto_pcibar = {
.set = set_enum,
.set_default_value = set_default_value_enum,
};
+
+/* --- PCIELinkSpeed 2_5/5/8/16 -- */
+
+static void get_prop_pcielinkspeed(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ DeviceState *dev = DEVICE(obj);
+ Property *prop = opaque;
+ PCIExpLinkSpeed *p = qdev_get_prop_ptr(dev, prop);
+ int speed;
+
+ switch (*p) {
+ case QEMU_PCI_EXP_LNK_2_5GT:
+ speed = PCIE_LINK_SPEED_2_5;
+ break;
+ case QEMU_PCI_EXP_LNK_5GT:
+ speed = PCIE_LINK_SPEED_5;
+ break;
+ case QEMU_PCI_EXP_LNK_8GT:
+ speed = PCIE_LINK_SPEED_8;
+ break;
+ case QEMU_PCI_EXP_LNK_16GT:
+ speed = PCIE_LINK_SPEED_16;
+ break;
+ default:
+ /* Unreachable */
+ abort();
+ }
+
+ visit_type_enum(v, prop->name, &speed, prop->info->enum_table, errp);
+}
+
+static void set_prop_pcielinkspeed(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ DeviceState *dev = DEVICE(obj);
+ Property *prop = opaque;
+ PCIExpLinkSpeed *p = qdev_get_prop_ptr(dev, prop);
+ int speed;
+ Error *local_err = NULL;
+
+ if (dev->realized) {
+ qdev_prop_set_after_realize(dev, name, errp);
+ return;
+ }
+
+ visit_type_enum(v, prop->name, &speed, prop->info->enum_table, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ switch (speed) {
+ case PCIE_LINK_SPEED_2_5:
+ *p = QEMU_PCI_EXP_LNK_2_5GT;
+ break;
+ case PCIE_LINK_SPEED_5:
+ *p = QEMU_PCI_EXP_LNK_5GT;
+ break;
+ case PCIE_LINK_SPEED_8:
+ *p = QEMU_PCI_EXP_LNK_8GT;
+ break;
+ case PCIE_LINK_SPEED_16:
+ *p = QEMU_PCI_EXP_LNK_16GT;
+ break;
+ default:
+ /* Unreachable */
+ abort();
+ }
+}
+
+const PropertyInfo qdev_prop_pcie_link_speed = {
+ .name = "PCIELinkSpeed",
+ .description = "2_5/5/8/16",
+ .enum_table = &PCIELinkSpeed_lookup,
+ .get = get_prop_pcielinkspeed,
+ .set = set_prop_pcielinkspeed,
+ .set_default_value = set_default_value_enum,
+};
+
+/* --- PCIELinkWidth 1/2/4/8/12/16/32 -- */
+
+static void get_prop_pcielinkwidth(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ DeviceState *dev = DEVICE(obj);
+ Property *prop = opaque;
+ PCIExpLinkWidth *p = qdev_get_prop_ptr(dev, prop);
+ int width;
+
+ switch (*p) {
+ case QEMU_PCI_EXP_LNK_X1:
+ width = PCIE_LINK_WIDTH_1;
+ break;
+ case QEMU_PCI_EXP_LNK_X2:
+ width = PCIE_LINK_WIDTH_2;
+ break;
+ case QEMU_PCI_EXP_LNK_X4:
+ width = PCIE_LINK_WIDTH_4;
+ break;
+ case QEMU_PCI_EXP_LNK_X8:
+ width = PCIE_LINK_WIDTH_8;
+ break;
+ case QEMU_PCI_EXP_LNK_X12:
+ width = PCIE_LINK_WIDTH_12;
+ break;
+ case QEMU_PCI_EXP_LNK_X16:
+ width = PCIE_LINK_WIDTH_16;
+ break;
+ case QEMU_PCI_EXP_LNK_X32:
+ width = PCIE_LINK_WIDTH_32;
+ break;
+ default:
+ /* Unreachable */
+ abort();
+ }
+
+ visit_type_enum(v, prop->name, &width, prop->info->enum_table, errp);
+}
+
+static void set_prop_pcielinkwidth(Object *obj, Visitor *v, const char *name,
+ void *opaque, Error **errp)
+{
+ DeviceState *dev = DEVICE(obj);
+ Property *prop = opaque;
+ PCIExpLinkWidth *p = qdev_get_prop_ptr(dev, prop);
+ int width;
+ Error *local_err = NULL;
+
+ if (dev->realized) {
+ qdev_prop_set_after_realize(dev, name, errp);
+ return;
+ }
+
+ visit_type_enum(v, prop->name, &width, prop->info->enum_table, &local_err);
+ if (local_err) {
+ error_propagate(errp, local_err);
+ return;
+ }
+
+ switch (width) {
+ case PCIE_LINK_WIDTH_1:
+ *p = QEMU_PCI_EXP_LNK_X1;
+ break;
+ case PCIE_LINK_WIDTH_2:
+ *p = QEMU_PCI_EXP_LNK_X2;
+ break;
+ case PCIE_LINK_WIDTH_4:
+ *p = QEMU_PCI_EXP_LNK_X4;
+ break;
+ case PCIE_LINK_WIDTH_8:
+ *p = QEMU_PCI_EXP_LNK_X8;
+ break;
+ case PCIE_LINK_WIDTH_12:
+ *p = QEMU_PCI_EXP_LNK_X12;
+ break;
+ case PCIE_LINK_WIDTH_16:
+ *p = QEMU_PCI_EXP_LNK_X16;
+ break;
+ case PCIE_LINK_WIDTH_32:
+ *p = QEMU_PCI_EXP_LNK_X32;
+ break;
+ default:
+ /* Unreachable */
+ abort();
+ }
+}
+
+const PropertyInfo qdev_prop_pcie_link_width = {
+ .name = "PCIELinkWidth",
+ .description = "1/2/4/8/12/16/32",
+ .enum_table = &PCIELinkWidth_lookup,
+ .get = get_prop_pcielinkwidth,
+ .set = set_prop_pcielinkwidth,
+ .set_default_value = set_default_value_enum,
+};
--
MST
- [Qemu-devel] [PULL v3 01/44] pcie: set link state inactive/active after hot unplug/plug, (continued)
- [Qemu-devel] [PULL v3 01/44] pcie: set link state inactive/active after hot unplug/plug, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 04/44] virtio: Provide version-specific variants of virtio PCI devices, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 03/44] virtio: Helper for registering virtio device types, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 05/44] tests: Remove unused include, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 06/44] hw/smbios: Restrict access to "hw/smbios/ipmi.h", Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 02/44] pc:piix4: Update smbus I/O space after a migration, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 09/44] hw/pci-bridge: Fix invalid free(), Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 07/44] hw/smbios: Remove "smbios_ipmi.h", Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 08/44] hw/smbios: Move to the hw/firmware/ subdirectory, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 10/44] pcie: Create enums for link speed and width, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 12/44] qapi: Define PCIe link speed and width properties,
Michael S. Tsirkin <=
- [Qemu-devel] [PULL v3 14/44] pcie: Fill PCIESlot link fields to support higher speeds and widths, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 13/44] pcie: Add link speed and width fields to PCIESlot, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 15/44] pcie: Allow generic PCIe root port to specify link speed and width, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 17/44] pcie: Fast PCIe root ports for new machines, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 11/44] pci: Sync PCIe downstream port LNKSTA on read, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 18/44] intel_iommu: dump correct iova when failed, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 19/44] intel_iommu: convert invalid traces into error reports, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 16/44] vfio/pci: Remove PCIe Link Status emulation, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 20/44] intel_iommu: dma read/write draining support, Michael S. Tsirkin, 2018/12/20
- [Qemu-devel] [PULL v3 21/44] intel_iommu: remove "x-" prefix for "aw-bits", Michael S. Tsirkin, 2018/12/20