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Re: [Qemu-devel] [PATCH 02/34] target/arm: Rely on optimization within t
From: |
David Gibson |
Subject: |
Re: [Qemu-devel] [PATCH 02/34] target/arm: Rely on optimization within tcg_gen_gvec_or |
Date: |
Wed, 19 Dec 2018 16:37:07 +1100 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
On Mon, Dec 17, 2018 at 10:38:39PM -0800, Richard Henderson wrote:
> Since we're now handling a == b generically, we no longer need
> to do it by hand within target/arm/.
>
> Signed-off-by: Richard Henderson <address@hidden>
Reviewed-by: David Gibson <address@hidden>
> ---
> target/arm/translate-a64.c | 6 +-----
> target/arm/translate-sve.c | 6 +-----
> target/arm/translate.c | 12 +++---------
> 3 files changed, 5 insertions(+), 19 deletions(-)
>
> diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
> index e1da1e4d6f..2d6f8c1b4f 100644
> --- a/target/arm/translate-a64.c
> +++ b/target/arm/translate-a64.c
> @@ -10152,11 +10152,7 @@ static void disas_simd_3same_logic(DisasContext *s,
> uint32_t insn)
> gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0);
> return;
> case 2: /* ORR */
> - if (rn == rm) { /* MOV */
> - gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_mov, 0);
> - } else {
> - gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0);
> - }
> + gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0);
> return;
> case 3: /* ORN */
> gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0);
> diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c
> index b15b615ceb..3a2eb51566 100644
> --- a/target/arm/translate-sve.c
> +++ b/target/arm/translate-sve.c
> @@ -280,11 +280,7 @@ static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz
> *a)
>
> static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
> {
> - if (a->rn == a->rm) { /* MOV */
> - return do_mov_z(s, a->rd, a->rn);
> - } else {
> - return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
> - }
> + return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
> }
>
> static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
> diff --git a/target/arm/translate.c b/target/arm/translate.c
> index 7c4675ffd8..33b1860148 100644
> --- a/target/arm/translate.c
> +++ b/target/arm/translate.c
> @@ -6294,15 +6294,9 @@ static int disas_neon_data_insn(DisasContext *s,
> uint32_t insn)
> tcg_gen_gvec_andc(0, rd_ofs, rn_ofs, rm_ofs,
> vec_size, vec_size);
> break;
> - case 2:
> - if (rn == rm) {
> - /* VMOV */
> - tcg_gen_gvec_mov(0, rd_ofs, rn_ofs, vec_size, vec_size);
> - } else {
> - /* VORR */
> - tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
> - vec_size, vec_size);
> - }
> + case 2: /* VORR */
> + tcg_gen_gvec_or(0, rd_ofs, rn_ofs, rm_ofs,
> + vec_size, vec_size);
> break;
> case 3: /* VORN */
> tcg_gen_gvec_orc(0, rd_ofs, rn_ofs, rm_ofs,
--
David Gibson | I'll have my music baroque, and my code
david AT gibson.dropbear.id.au | minimalist, thank you. NOT _the_ _other_
| _way_ _around_!
http://www.ozlabs.org/~dgibson
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- Re: [Qemu-devel] [PATCH 22/34] target/ppc: convert VSX logical operations to vector operations, (continued)
- [Qemu-devel] [PATCH 30/34] target/ppc: Use mtvscr/mfvscr for vmstate, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 18/34] target/ppc: convert vaddu[b, h, w, d] and vsubu[b, h, w, d] over to use vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 32/34] target/ppc: Split out VSCR_SAT to a vector field, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 34/34] target/ppc: convert vmin* and vmax* to vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 02/34] target/arm: Rely on optimization within tcg_gen_gvec_or, Richard Henderson, 2018/12/18
- Re: [Qemu-devel] [PATCH 02/34] target/arm: Rely on optimization within tcg_gen_gvec_or,
David Gibson <=
- [Qemu-devel] [PATCH 14/34] target/ppc: switch FPR, VMX and VSX helpers to access data directly from cpu_env, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 27/34] target/ppc: Use helper_mtvscr for reset and gdb, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 29/34] target/ppc: Add helper_mfvscr, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 07/34] tcg: Add opcodes for vector minmax arithmetic, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 33/34] target/ppc: convert vadd*s and vsub*s to vector operations, Richard Henderson, 2018/12/18
- [Qemu-devel] [PATCH 23/34] target/ppc: convert xxspltib to vector operations, Richard Henderson, 2018/12/18