Re: [Qemu-devel] [PATCH v5 6/8] pcie: Allow generic PCIe root port to specify link speed and width

[Michael S. Tsirkin]

On Wed, Dec 12, 2018 at 12:39:43PM -0700, Alex Williamson wrote:
> Allow users to experimentally specify speed and width values for the
> generic PCIe root port.  Defaults remain at 2.5GT/s & x1 for
> compatiblity with the intent to only support changing defaults via
> machine types for now.
> 
> Note for libvirt testing that pcie-root-port controllers are given
> default names like "pci.7" which don't play well with using the
> "-set device.$name.$prop=$value" options accessible to us via
> <qemu:commandline> options.  The solution is to add an <alias> to the
> pcie-root-port <controller>, for example:
> 
>     <controller type='pci' index='7' model='pcie-root-port'>
>       <model name='pcie-root-port'/>
>       <target chassis='7' port='0x15'/>
>       <alias name='ua-gfx0'/>
>       <address type='pci' domain='0x0000' bus='0x00' slot='0x02' 
> function='0x5'/>
>     </controller>
> 
> The "ua-" here is a mandatory prefix.  We can then use:
> 
>   <qemu:commandline>
>     <qemu:arg value='-set'/>
>     <qemu:arg value='device.ua-gfx0.x-speed=8'/>
>     <qemu:arg value='-set'/>
>     <qemu:arg value='device.ua-gfx0.x-width=16'/>
>   </qemu:commandline>
> 
> or, without an alias, set globals such as:
> 
>   <qemu:commandline>
>     <qemu:arg value='-global'/>
>     <qemu:arg value='pcie-root-port.x-speed=8'/>
>     <qemu:arg value='-global'/>
>     <qemu:arg value='pcie-root-port.x-width=16'/>
>   </qemu:commandline>
> 
> Cc: Michael S. Tsirkin <address@hidden>
> Cc: Marcel Apfelbaum <address@hidden>
> Tested-by: Geoffrey McRae <address@hidden>
> Reviewed-by: Eric Auger <address@hidden>
> Signed-off-by: Alex Williamson <address@hidden>
> ---
>  hw/pci-bridge/gen_pcie_root_port.c |    4 ++++
>  1 file changed, 4 insertions(+)
> 
> diff --git a/hw/pci-bridge/gen_pcie_root_port.c 
> b/hw/pci-bridge/gen_pcie_root_port.c
> index 299de429ec1e..ca5418a89dd2 100644
> --- a/hw/pci-bridge/gen_pcie_root_port.c
> +++ b/hw/pci-bridge/gen_pcie_root_port.c
> @@ -124,6 +124,10 @@ static Property gen_rp_props[] = {
>                       res_reserve.mem_pref_32, -1),
>      DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
>                       res_reserve.mem_pref_64, -1),
> +    DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
> +                                speed, PCIE_LINK_SPEED_2_5),
> +    DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
> +                                width, PCIE_LINK_WIDTH_1),
>      DEFINE_PROP_END_OF_LIST()
>  };
>  

Doesn't seem to build.
Just where is DEFINE_PROP_PCIE_LINK_SPEED defined?

-- 
MST