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[Qemu-devel] [PATCH 17/26] target/arm: Reuse aa64_va_parameters for sett
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH 17/26] target/arm: Reuse aa64_va_parameters for setting tbflags |
Date: |
Fri, 7 Dec 2018 04:36:22 -0600 |
The arm_regime_tbi{0,1} functions are replacable with the new function
by giving the lowest and highest address.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.h | 35 -----------------------------
target/arm/helper.c | 55 +++++++++------------------------------------
2 files changed, 10 insertions(+), 80 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 6bac5c18d0..f7a0eace68 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -3065,41 +3065,6 @@ static inline bool arm_cpu_bswap_data(CPUARMState *env)
}
#endif
-#ifndef CONFIG_USER_ONLY
-/**
- * arm_regime_tbi0:
- * @env: CPUARMState
- * @mmu_idx: MMU index indicating required translation regime
- *
- * Extracts the TBI0 value from the appropriate TCR for the current EL
- *
- * Returns: the TBI0 value.
- */
-uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx);
-
-/**
- * arm_regime_tbi1:
- * @env: CPUARMState
- * @mmu_idx: MMU index indicating required translation regime
- *
- * Extracts the TBI1 value from the appropriate TCR for the current EL
- *
- * Returns: the TBI1 value.
- */
-uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx);
-#else
-/* We can't handle tagged addresses properly in user-only mode */
-static inline uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
- return 0;
-}
-
-static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
- return 0;
-}
-#endif
-
void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
target_ulong *cs_base, uint32_t *flags);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 99ceed2cab..3ad5909b1e 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8967,48 +8967,6 @@ static inline ARMMMUIdx stage_1_mmu_idx(ARMMMUIdx
mmu_idx)
return mmu_idx;
}
-/* Returns TBI0 value for current regime el */
-uint32_t arm_regime_tbi0(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
- TCR *tcr;
- uint32_t el;
-
- /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
- * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
- */
- mmu_idx = stage_1_mmu_idx(mmu_idx);
-
- tcr = regime_tcr(env, mmu_idx);
- el = regime_el(env, mmu_idx);
-
- if (el > 1) {
- return extract64(tcr->raw_tcr, 20, 1);
- } else {
- return extract64(tcr->raw_tcr, 37, 1);
- }
-}
-
-/* Returns TBI1 value for current regime el */
-uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx)
-{
- TCR *tcr;
- uint32_t el;
-
- /* For EL0 and EL1, TBI is controlled by stage 1's TCR, so convert
- * a stage 1+2 mmu index into the appropriate stage 1 mmu index.
- */
- mmu_idx = stage_1_mmu_idx(mmu_idx);
-
- tcr = regime_tcr(env, mmu_idx);
- el = regime_el(env, mmu_idx);
-
- if (el > 1) {
- return 0;
- } else {
- return extract64(tcr->raw_tcr, 38, 1);
- }
-}
-
/* Return the TTBR associated with this translation regime */
static inline uint64_t regime_ttbr(CPUARMState *env, ARMMMUIdx mmu_idx,
int ttbrn)
@@ -13041,9 +12999,16 @@ void cpu_get_tb_cpu_state(CPUARMState *env,
target_ulong *pc,
*pc = env->pc;
flags = ARM_TBFLAG_AARCH64_STATE_MASK;
- /* Get control bits for tagged addresses */
- flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT);
- flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT);
+
+#ifndef CONFIG_USER_ONLY
+ /* Get control bits for tagged addresses. Note that the
+ * translator only uses this for instruction addresses.
+ */
+ flags |= (aa64_va_parameters(env, 0, mmu_idx, false).tbi
+ << ARM_TBFLAG_TBI0_SHIFT);
+ flags |= (aa64_va_parameters(env, -1, mmu_idx, false).tbi
+ << ARM_TBFLAG_TBI1_SHIFT);
+#endif
if (cpu_isar_feature(aa64_sve, cpu)) {
int sve_el = sve_exception_el(env, current_el);
--
2.17.2
- [Qemu-devel] [PATCH 10/26] target/arm: Add new_pc argument to helper_exception_return, (continued)
- [Qemu-devel] [PATCH 10/26] target/arm: Add new_pc argument to helper_exception_return, Richard Henderson, 2018/12/07
- [Qemu-devel] [PATCH 11/26] target/arm: Rearrange decode in disas_uncond_b_reg, Richard Henderson, 2018/12/07
- [Qemu-devel] [PATCH 15/26] target/arm: Introduce arm_mmu_idx, Richard Henderson, 2018/12/07
- [Qemu-devel] [PATCH 13/26] target/arm: Decode Load/store register (pac), Richard Henderson, 2018/12/07
- [Qemu-devel] [PATCH 12/26] target/arm: Decode PAuth within disas_uncond_b_reg, Richard Henderson, 2018/12/07
- [Qemu-devel] [PATCH 14/26] target/arm: Move cpu_mmu_index out of line, Richard Henderson, 2018/12/07
- [Qemu-devel] [PATCH 17/26] target/arm: Reuse aa64_va_parameters for setting tbflags,
Richard Henderson <=
- [Qemu-devel] [PATCH 18/26] target/arm: Export aa64_va_parameters to internals.h, Richard Henderson, 2018/12/07
- [Qemu-devel] [PATCH 19/26] target/arm: Implement pauth_strip, Richard Henderson, 2018/12/07
- [Qemu-devel] [PATCH 20/26] target/arm: Implement pauth_auth, Richard Henderson, 2018/12/07
- [Qemu-devel] [PATCH 16/26] target/arm: Create ARMVAParameters and helpers, Richard Henderson, 2018/12/07
- [Qemu-devel] [PATCH 21/26] target/arm: Implement pauth_addpac, Richard Henderson, 2018/12/07