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Re: [Qemu-devel] [PATCH v9 08/14] target/arm: Make PMCEID[01]_EL0 64 bit
From: |
Peter Maydell |
Subject: |
Re: [Qemu-devel] [PATCH v9 08/14] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23] |
Date: |
Thu, 6 Dec 2018 15:59:05 +0000 |
On Wed, 5 Dec 2018 at 15:32, Aaron Lindsay <address@hidden> wrote:
>
> On Dec 05 08:43, Aaron Lindsay wrote:
> > Signed-off-by: Aaron Lindsay <address@hidden>
> > ---
> > target/arm/cpu.h | 4 ++--
> > target/arm/helper.c | 18 ++++++++++++++++--
> > 2 files changed, 18 insertions(+), 4 deletions(-)
> >
> > diff --git a/target/arm/cpu.h b/target/arm/cpu.h
> > index 304e6e47b3..4216fe22db 100644
> > --- a/target/arm/cpu.h
> > +++ b/target/arm/cpu.h
> > @@ -837,8 +837,8 @@ struct ARMCPU {
> > uint32_t id_pfr0;
> > uint32_t id_pfr1;
> > uint32_t id_dfr0;
> > - uint32_t pmceid0;
> > - uint32_t pmceid1;
> > + uint64_t pmceid0;
> > + uint64_t pmceid1;
> > uint32_t id_afr0;
> > uint32_t id_mmfr0;
> > uint32_t id_mmfr1;
> > diff --git a/target/arm/helper.c b/target/arm/helper.c
> > index 71be6fb578..fb6939e99c 100644
> > --- a/target/arm/helper.c
> > +++ b/target/arm/helper.c
> > @@ -5256,6 +5256,20 @@ void register_cp_regs_for_features(ARMCPU *cpu)
> > } else {
> > define_arm_cp_regs(cpu, not_v7_cp_reginfo);
> > }
> > + if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4) {
>
> After further discussion on my last version, this should be
>
> if (FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) >= 4 &&
> FIELD_EX32(cpu->id_dfr0, ID_DFR0, PERFMON) != 0xf) {
>
> to guard against defining these registers for implementation-defined
> PMUs.
With that change
Reviewed-by: Peter Maydell <address@hidden>
thanks
-- PMM
- [Qemu-devel] [PATCH v9 04/14] target/arm: Filter cycle counter based on PMCCFILTR_EL0, (continued)
- [Qemu-devel] [PATCH v9 04/14] target/arm: Filter cycle counter based on PMCCFILTR_EL0, Aaron Lindsay, 2018/12/05
- [Qemu-devel] [PATCH v9 02/14] target/arm: Reorganize PMCCNTR accesses, Aaron Lindsay, 2018/12/05
- [Qemu-devel] [PATCH v9 05/14] target/arm: Allow AArch32 access for PMCCFILTR, Aaron Lindsay, 2018/12/05
- [Qemu-devel] [PATCH v9 06/14] target/arm: Implement PMOVSSET, Aaron Lindsay, 2018/12/05
- [Qemu-devel] [PATCH v9 07/14] target/arm: Define FIELDs for ID_DFR0, Aaron Lindsay, 2018/12/05
- [Qemu-devel] [PATCH v9 09/14] target/arm: Add array for supported PMU events, generate PMCEID[01]_EL0, Aaron Lindsay, 2018/12/05
- [Qemu-devel] [PATCH v9 12/14] target/arm: PMU: Set PMCR.N to 4, Aaron Lindsay, 2018/12/05
- [Qemu-devel] [PATCH v9 08/14] target/arm: Make PMCEID[01]_EL0 64 bit registers, add PMCEID[23], Aaron Lindsay, 2018/12/05
- [Qemu-devel] [PATCH v9 11/14] target/arm: PMU: Add instruction and cycle events, Aaron Lindsay, 2018/12/05
- [Qemu-devel] [PATCH v9 10/14] target/arm: Finish implementation of PM[X]EVCNTR and PM[X]EVTYPER, Aaron Lindsay, 2018/12/05
- [Qemu-devel] [PATCH v9 13/14] target/arm: Implement PMSWINC, Aaron Lindsay, 2018/12/05
- [Qemu-devel] [PATCH v9 14/14] target/arm: Send interrupts on PMU counter overflow, Aaron Lindsay, 2018/12/05