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[Qemu-devel] [PATCH v2 07/10] target/arm: Tidy scr_write
From: |
Richard Henderson |
Subject: |
[Qemu-devel] [PATCH v2 07/10] target/arm: Tidy scr_write |
Date: |
Mon, 3 Dec 2018 14:38:36 -0600 |
Because EL3 has a fixed execution mode, we can properly decide
which of the bits are RES{0,1}.
Signed-off-by: Richard Henderson <address@hidden>
---
target/arm/cpu.h | 2 --
target/arm/helper.c | 14 +++++++++-----
2 files changed, 9 insertions(+), 7 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index e871b946c8..a84101efa9 100644
--- a/target/arm/cpu.h
+++ b/target/arm/cpu.h
@@ -1312,8 +1312,6 @@ static inline void xpsr_write(CPUARMState *env, uint32_t
val, uint32_t mask)
#define SCR_FIEN (1U << 21)
#define SCR_ENSCXT (1U << 25)
#define SCR_ATA (1U << 26)
-#define SCR_AARCH32_MASK (0x3fff & ~(SCR_RW | SCR_ST))
-#define SCR_AARCH64_MASK (0x3fff & ~SCR_NET)
/* Return the current FPSCR value. */
uint32_t vfp_get_fpscr(CPUARMState *env);
diff --git a/target/arm/helper.c b/target/arm/helper.c
index b248dfcd39..faf7f922bf 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1279,11 +1279,15 @@ static void vbar_write(CPUARMState *env, const
ARMCPRegInfo *ri,
static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
{
- /* We only mask off bits that are RES0 both for AArch64 and AArch32.
- * For bits that vary between AArch32/64, code needs to check the
- * current execution mode before directly using the feature bit.
- */
- uint32_t valid_mask = SCR_AARCH64_MASK | SCR_AARCH32_MASK;
+ /* Begin with base v8.0 state. */
+ uint32_t valid_mask = 0x3fff;
+
+ if (arm_el_is_aa64(env, 3)) {
+ value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
+ valid_mask &= ~SCR_NET;
+ } else {
+ valid_mask &= ~(SCR_RW | SCR_ST);
+ }
if (!arm_feature(env, ARM_FEATURE_EL2)) {
valid_mask &= ~SCR_HCE;
--
2.17.2
- [Qemu-devel] [PATCH v2 04/10] target/arm: Fix HCR_EL2.TGE check in arm_phys_excp_target_el, (continued)
- [Qemu-devel] [PATCH v2 09/10] target/arm: Implement the ARMv8.1-HPD extension, Richard Henderson, 2018/12/03
- [Qemu-devel] [PATCH v2 07/10] target/arm: Tidy scr_write,
Richard Henderson <=
- [Qemu-devel] [PATCH v2 10/10] target/arm: Implement the ARMv8.2-AA32HPD extension, Richard Henderson, 2018/12/03
- [Qemu-devel] [PATCH v2 08/10] target/arm: Implement the ARMv8.1-LOR extension, Richard Henderson, 2018/12/03
- Re: [Qemu-devel] [PATCH v2 00/10] target/arm: LOR, HPD, AA32HPD, Peter Maydell, 2018/12/06