Re: [Qemu-devel] [PATCH] Add Alistair as a RISC-V Maintainer

[Philippe Mathieu-Daudé]

On Tue, Oct 30, 2018 at 4:04 PM Peter Maydell <address@hidden> wrote:
>
> On 29 October 2018 at 18:41, Palmer Dabbelt <address@hidden> wrote:
> > On Mon, 29 Oct 2018 10:59:47 PDT (-0700), Peter Maydell wrote:
> >>
> >> On 29 October 2018 at 17:14, Palmer Dabbelt <address@hidden> wrote:
> >>>
> >>> I don't think we have anything ready to go right now: your PCIe patches
> >>> still have some outstanding feedback (on interrupt stuff), and Bastian's
> >>> decodetree stuff has some patches from Richard Henderson that should be
> >>> merged in.  I was hoping to get through reviewing Michael's patches to
> >>> fix
> >>> the FS dirty bit, but haven't had time yet -- they're tested, but I
> >>> haven't
> >>> actually read through them.
> >>>
> >>> Maybe we should get a RISC-V QEMU mailing list so we can keep everyone in
> >>> sync without spamming the whole world?
> >>
> >>
> >> We can sort out a qemu-riscv mailing list like the ones we have
> >> for ppc and arm if you like:
> >> https://wiki.qemu.org/Contribute/MailingLists
> >
> >
> > I think that'd be good.  It makes things a bit easier on my end as I can
> > ensure I don't miss any patches that end up on our list.
>
> OK, I have set one up. The subscription page is at:
> https://lists.nongnu.org/mailman/listinfo/qemu-riscv

Thanks!

> I think I have got the list config correct but let me know if you
> notice anything weird.

http://lists.nongnu.org/archive/html/qemu-riscv/ returns 404 Not
found: The requested URL /archive/html/qemu-riscv/ was not found on
this server.

This might be a cron job and I need to wait.

>
> I suggest submitting a patch to MAINTAINERS that adds an
> L: address@hidden
> line to the RISC-V section of that file.
>
> thanks
> -- PMM
>