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Re: [Qemu-devel] [PATCH 0/4] target/arm: Minimize TLB flushing for ASID
From: |
Emilio G. Cota |
Subject: |
Re: [Qemu-devel] [PATCH 0/4] target/arm: Minimize TLB flushing for ASID changes |
Date: |
Tue, 30 Oct 2018 11:40:41 -0400 |
User-agent: |
Mutt/1.9.4 (2018-02-28) |
On Mon, Oct 29, 2018 at 15:53:35 +0000, Richard Henderson wrote:
> In http://lists.nongnu.org/archive/html/qemu-devel/2018-10/msg04181.html
> (already upstream) I added a check for ASID changes without realizing
> that TTBCR_EL1 has the A1 bit, controlling which register actually
> contains the active ASID.
>
> In http://lists.nongnu.org/archive/html/qemu-devel/2018-10/msg04182.html
> I suggested a set of mmu_idx to flush when the ASID does change. In
> follow-up, Peter suggested more.
>
> I now choose secure vs non-secure mmu_idx based on which register is being
> modified, not the current state of the cpu. Unless I am mistaken, secure
> state can write to the non-secure registers. Which means that the current
> state of the cpu is irrelevant and only the register matters.
>
> Peter suggested flushing S1E3 when changing ttbr0_s. I can see how this
> is overlapped onto the EL3 (Secure Monitor) state, but I cannot see how
> the ASID is used from EL3. The best evidence I can find for this is that
> there is no TLBIASID* register that is applicable to flushing EL3; that's
> not conclusive proof though. So while I'm not sure it's necessary, I'm
> also not sure it isn't necessary, and so I've included S1E3 in the flush.
>
> I now also use the VMID to conditionally invalidate the stage 2 translation
> state. This shows how I anticipaged @depmap to be used in patch 1.
I've tested this series and the one it depends on (tlb-dirty). I had
yesterday a guest running parallel compilation jobs for ~12h with
no issues. So
Tested-by: Emilio G. Cota <address@hidden>
for this and the tlb-dirty series.
Richard: the crash I reported on IRC must have been due to unrelated
changes. I was testing some TLB experiments over the weekend so I must
have forgotten to rebuild.
Thanks,
Emilio