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[Qemu-devel] [PULL 17/27] target/mips: Add emulation of MXU instruction
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 17/27] target/mips: Add emulation of MXU instruction D16MAC |
Date: |
Mon, 29 Oct 2018 16:20:08 +0100 |
From: Craig Janeczek <address@hidden>
Add support for emulating the D16MAC MXU instruction.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 90 +++++++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 87 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index dbcb69b..4777228 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24237,6 +24237,92 @@ static void gen_mxu_d16mul(DisasContext *ctx)
tcg_temp_free(t3);
}
+/*
+ * D16MAC XRa, XRb, XRc, XRd, aptn2, optn2 - Signed 16 bit pattern multiply
+ * and accumulate
+ */
+static void gen_mxu_d16mac(DisasContext *ctx)
+{
+ TCGv t0, t1, t2, t3;
+ TCGLabel *l0;
+ uint32_t XRa, XRb, XRc, XRd, optn2, aptn2;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ t2 = tcg_temp_new();
+ t3 = tcg_temp_new();
+
+ l0 = gen_new_label();
+
+ XRa = extract32(ctx->opcode, 6, 4);
+ XRb = extract32(ctx->opcode, 10, 4);
+ XRc = extract32(ctx->opcode, 14, 4);
+ XRd = extract32(ctx->opcode, 18, 4);
+ optn2 = extract32(ctx->opcode, 22, 2);
+ aptn2 = extract32(ctx->opcode, 24, 2);
+
+ gen_load_mxu_cr(t0);
+ tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
+
+ gen_load_mxu_gpr(t1, XRb);
+ tcg_gen_sextract_tl(t0, t1, 0, 16);
+ tcg_gen_sextract_tl(t1, t1, 16, 16);
+
+ gen_load_mxu_gpr(t3, XRc);
+ tcg_gen_sextract_tl(t2, t3, 0, 16);
+ tcg_gen_sextract_tl(t3, t3, 16, 16);
+
+ switch (optn2) {
+ case MXU_OPTN2_WW: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */
+ tcg_gen_mul_tl(t3, t1, t3);
+ tcg_gen_mul_tl(t2, t0, t2);
+ break;
+ case MXU_OPTN2_LW: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */
+ tcg_gen_mul_tl(t3, t0, t3);
+ tcg_gen_mul_tl(t2, t0, t2);
+ break;
+ case MXU_OPTN2_HW: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */
+ tcg_gen_mul_tl(t3, t1, t3);
+ tcg_gen_mul_tl(t2, t1, t2);
+ break;
+ case MXU_OPTN2_XW: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */
+ tcg_gen_mul_tl(t3, t0, t3);
+ tcg_gen_mul_tl(t2, t1, t2);
+ break;
+ }
+ gen_load_mxu_gpr(t0, XRa);
+ gen_load_mxu_gpr(t1, XRd);
+
+ switch (aptn2) {
+ case MXU_APTN2_AA:
+ tcg_gen_add_tl(t3, t0, t3);
+ tcg_gen_add_tl(t2, t1, t2);
+ break;
+ case MXU_APTN2_AS:
+ tcg_gen_add_tl(t3, t0, t3);
+ tcg_gen_sub_tl(t2, t1, t2);
+ break;
+ case MXU_APTN2_SA:
+ tcg_gen_sub_tl(t3, t0, t3);
+ tcg_gen_add_tl(t2, t1, t2);
+ break;
+ case MXU_APTN2_SS:
+ tcg_gen_sub_tl(t3, t0, t3);
+ tcg_gen_sub_tl(t2, t1, t2);
+ break;
+ }
+ gen_store_mxu_gpr(t3, XRa);
+ gen_store_mxu_gpr(t2, XRd);
+
+ gen_set_label(l0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+ tcg_temp_free(t3);
+}
+
/*
* Decoding engine for MXU
@@ -25207,9 +25293,7 @@ static void decode_opc_mxu(CPUMIPSState *env,
DisasContext *ctx)
decode_opc_mxu__pool03(env, ctx);
break;
case OPC_MXU_D16MAC:
- /* TODO: Implement emulation of D16MAC instruction. */
- MIPS_INVAL("OPC_MXU_D16MAC");
- generate_exception_end(ctx, EXCP_RI);
+ gen_mxu_d16mac(ctx);
break;
case OPC_MXU_D16MACF:
/* TODO: Implement emulation of D16MACF instruction. */
--
2.7.4
- [Qemu-devel] [PULL 10/27] target/mips: Add bit encoding for MXU operand getting pattern 'optn2', (continued)
- [Qemu-devel] [PULL 10/27] target/mips: Add bit encoding for MXU operand getting pattern 'optn2', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 25/27] linux-user: Read and set FP ABI value from MIPS abiflags, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 22/27] elf: Define MIPS_ABI_FP_UNKNOWN macro, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 16/27] target/mips: Add emulation of MXU instruction D16MUL, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 11/27] target/mips: Add bit encoding for MXU operand getting pattern 'optn3', Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 15/27] target/mips: Add emulation of MXU instruction S8LDD, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 26/27] linux-user: Determine the desired FPU mode from MIPS.abiflags, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 24/27] linux-user: Extract MIPS abiflags from ELF file, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 18/27] target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 14/27] target/mips: Move MUL, S32M2I, S32I2M handling out of main MXU switch, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 17/27] target/mips: Add emulation of MXU instruction D16MAC,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 13/27] target/mips: Add emulation of MXU instructions S32I2M and S32M2I, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 04/27] target/mips: Amend MXU instruction opcodes, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 20/27] target/mips: Move MXU_EN check one level higher, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 21/27] target/mips: Amend MXU ASE overview note, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 19/27] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 23/27] linux-user: Extend image_info struct with MIPS fp_abi and interp_fp_abi fields, Aleksandar Markovic, 2018/10/29
- [Qemu-devel] [PULL 27/27] linux-user: Add prctl() PR_SET_FP_MODE and PR_GET_FP_MODE implementations, Aleksandar Markovic, 2018/10/29
- Re: [Qemu-devel] [PULL 00/27] MIPS queue for October 2018, part 4, Peter Maydell, 2018/10/30