Re: [Qemu-devel] [PATCH v2] strongarm: mask off high[32:28] bits from dir and state registers

[Peter Maydell]

On 26 October 2018 at 08:30, P J P <address@hidden> wrote:
> From: Prasad J Pandit <address@hidden>
>
> The high[32:28] bits of 'direction' and 'state' registers of
> SA-1100/SA-1110 device are reserved. Setting them may lead to
> OOB 's->handler[]' array access issue. Mask off [32:28] bits to
> avoid it.

There is no bit 32 in a 32-bit value; you mean 31.

>
> Reported-by: Moguofang <address@hidden>
> Signed-off-by: Prasad J Pandit <address@hidden>
> ---
>  hw/arm/strongarm.c | 4 ++--
>  1 file changed, 2 insertions(+), 2 deletions(-)
>
> Update v2: mask off high[32:28] bits
>   -> https://lists.gnu.org/archive/html/qemu-devel/2018-10/msg05746.html
>
> diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c
> index ec2627374d..dd8c4b1f2e 100644
> --- a/hw/arm/strongarm.c
> +++ b/hw/arm/strongarm.c
> @@ -587,12 +587,12 @@ static void strongarm_gpio_write(void *opaque, hwaddr 
> offset,
>
>      switch (offset) {
>      case GPDR:        /* GPIO Pin-Direction registers */
> -        s->dir = value;
> +        s->dir = value & 0x3fffff;

The commit message says it's masking [31:28], but the
code is masking [31:22]. The SA1110 spec suggests the
commit message is correct and the code is not.

thanks
-- PMM