Re: [Qemu-devel] a64 simd decode in handle_vec_simd_shli()

[Peter Maydell]

On 29 October 2018 at 12:32, Richard Henderson
<address@hidden> wrote:
> On 10/29/18 12:06 PM, Peter Maydell wrote:
>> I'm having difficulty figuring out where this check has come from;
>> it doesn't seem to match up with the pseudocode and in any case
>> I don't think size can ever be > 3. We calculate:
>>
>>     int size = 32 - clz32(immh) - 1;
>> where immh is a 4 bit field which we know cannot be all-zeroes.
>> So the clz32() return must be in {28,29,30,31} and the resulting
>> size is in {0,1,2,3}, so the check above can't ever fire.
>
> Correct.
>
> The check appeared with the initial commit for aa64 support, so perhaps Alex
> just trying to be defensive in his coding?
>
>> Am I missing something? As far as I can see we should simply delete
>> the can't-happen condition, which will probably satisfy coverity.
>
> Agreed.

As assert that size is in [0..3] would probably be reasonable too,
since the thing that requires it (that the immh field is 4-bit non-zero)
is something implicitly determined by the decode so it's a bit
action-at-a-distance. I'll put together a patch.

thanks
-- PMM