On Sat, 20 Oct 2018 00:14:22 PDT (-0700),
address@hidden wrote:
Hi,
this patchset converts the RISC-V decoder to decodetree in three
major steps:
1) Convert 32-bit instructions to decodetree [Patch 1-14]:
Many of the gen_* functions are called by the decode functions
for 16-bit
and 32-bit functions. If we move translation code from the gen_*
functions to the generated trans_* functions of decode-tree, we
get a lot of
duplication. Therefore, we mostly generate calls to the old gen_*
function
which are properly replaced after step 2).
Each of the trans_ functions are grouped into files corresponding
to their
ISA extension, e.g. addi which is in RV32I is translated in the file
'trans_rvi.inc.c'.
2) Convert 16-bit instructions to decodetree [Patch 15-17]:
All 16 bit instructions have a direct mapping to a 32 bit
instruction. Thus,
we convert the arguments in the 16 bit trans_ function to the
arguments of
the corresponding 32 bit instruction and call the 32 bit trans_
function.
3) Remove old manual decoding in gen_* function [Patch 17-28]:
this move all manual translation code into the trans_*
instructions of
decode tree, such that we can remove the old decode_* functions.
the full tree can be found here:
https://github.com/bkoppelmann/qemu/tree/riscv-dt-v2
Thanks!
I dropped this on top of master and it appears I'm getting a bunch of
oops when trying to boot Linux. They're fairly far into the boot
process and may be a mistake on my end, I was just wondering if you'd
booted Linux?