[Date Prev][Date Next][Thread Prev][Thread Next][Date Index][Thread Index]
[Qemu-devel] [PATCH 06/11] tests/tcg/mips: Test R5900 three-operand MADD
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH 06/11] tests/tcg/mips: Test R5900 three-operand MADD1 |
Date: |
Thu, 25 Oct 2018 19:32:50 +0200 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
Signed-off-by: Fredrik Noring <address@hidden>
---
tests/tcg/mips/mipsr5900/madd.c | 43 +++++++++++++++++++++++++++++----
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/madd.c b/tests/tcg/mips/mipsr5900/madd.c
index 9ad2ea6dbb..f6f215e1c3 100644
--- a/tests/tcg/mips/mipsr5900/madd.c
+++ b/tests/tcg/mips/mipsr5900/madd.c
@@ -1,5 +1,5 @@
/*
- * Test R5900-specific three-operand MADD.
+ * Test R5900-specific three-operand MADD and MADD1.
*/
#include <stdio.h>
@@ -29,12 +29,45 @@ int64_t madd(int64_t a, int32_t rs, int32_t rt)
return r;
}
+int64_t madd1(int64_t a, int32_t rs, int32_t rt)
+{
+ int32_t lo = a;
+ int32_t hi = a >> 32;
+ int32_t rd;
+ int64_t r;
+
+ __asm__ __volatile__ (
+ " mtlo1 %5\n"
+ " mthi1 %6\n"
+ " madd1 %0, %3, %4\n"
+ " mflo1 %1\n"
+ " mfhi1 %2\n"
+ : "=r" (rd), "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt), "r" (lo), "r" (hi));
+ r = ((int64_t)hi << 32) | (uint32_t)lo;
+
+ assert(a + (int64_t)rs * rt == r);
+ assert(rd == lo);
+
+ return r;
+}
+
+static int64_t madd_variants(int64_t a, int32_t rs, int32_t rt)
+{
+ int64_t rd = madd(a, rs, rt);
+ int64_t rd1 = madd1(a, rs, rt);
+
+ assert(rd == rd1);
+
+ return rd;
+}
+
static void verify_madd(int64_t a, int32_t rs, int32_t rt, int64_t expected)
{
- assert(madd(a, rs, rt) == expected);
- assert(madd(a, -rs, rt) == a + a - expected);
- assert(madd(a, rs, -rt) == a + a - expected);
- assert(madd(a, -rs, -rt) == expected);
+ assert(madd_variants(a, rs, rt) == expected);
+ assert(madd_variants(a, -rs, rt) == a + a - expected);
+ assert(madd_variants(a, rs, -rt) == a + a - expected);
+ assert(madd_variants(a, -rs, -rt) == expected);
}
int main()
--
2.18.1
- [Qemu-devel] [PATCH 00/11] target/mips: Amend R5900 support, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 01/11] target/mips: Rename ASE_MMI to ASE_TOSHIBA_MMI, with Toshiba namespace, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 02/11] target/mips: R5900 LQ and SQ also belong to the Toshiba MMI ASE, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 03/11] target/mips: Support Toshiba specific three-operand MADD and MADDU, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 04/11] target/mips: Support R5900 three-operand MADD1 and MADDU1, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 05/11] tests/tcg/mips: Test R5900 three-operand MADD, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 06/11] tests/tcg/mips: Test R5900 three-operand MADD1,
Fredrik Noring <=
- [Qemu-devel] [PATCH 07/11] tests/tcg/mips: Test R5900 three-operand MADDU, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 08/11] tests/tcg/mips: Test R5900 three-operand MADDU1, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 09/11] disas/mips: Increase 'member of ISAs' flag holder size, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 10/11] disas/mips: Define R5900 disassembly constants, Fredrik Noring, 2018/10/25
- [Qemu-devel] [PATCH 11/11] disas/mips: Disassemble R5900 DIV[U]1, M{F, T}{LO, HI}1 and MULT[U]1, Fredrik Noring, 2018/10/25