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[Qemu-devel] [PULL 11/34] target/mips: Placeholder for R5900 LQ
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 11/34] target/mips: Placeholder for R5900 LQ |
Date: |
Mon, 22 Oct 2018 14:57:34 +0200 |
From: Fredrik Noring <address@hidden>
Add a placeholder for LQ instruction.
Reviewed-by: Aleksandar Markovic <address@hidden>
Signed-off-by: Fredrik Noring <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 13 +++++++++++--
1 file changed, 11 insertions(+), 2 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 19a8aba..2318116 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -24420,6 +24420,11 @@ static void decode_opc_special3_legacy(CPUMIPSState
*env, DisasContext *ctx)
}
}
+static void decode_tx79_lq(CPUMIPSState *env, DisasContext *ctx)
+{
+ generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_LQ */
+}
+
static void gen_tx79_sq(DisasContext *ctx, int base, int rt, int offset)
{
generate_exception_end(ctx, EXCP_RI); /* TODO: TX79_SQ */
@@ -26425,8 +26430,12 @@ static void decode_opc(CPUMIPSState *env, DisasContext
*ctx)
}
break;
case OPC_MSA: /* OPC_MDMX */
- /* MDMX: Not implemented. */
- gen_msa(env, ctx);
+ if (ctx->insn_flags & INSN_R5900) {
+ decode_tx79_lq(env, ctx); /* TX79_LQ */
+ } else {
+ /* MDMX: Not implemented. */
+ gen_msa(env, ctx);
+ }
break;
case OPC_PCREL:
check_insn(ctx, ISA_MIPS32R6);
--
2.7.4
- [Qemu-devel] [PULL 00/34] MIPS queue for October 2018 - part 2, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 01/34] target/mips: Define R5900 ISA, MMI ASE, and R5900 CPU preprocessor constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 02/34] disas/mips: Define R5900 disassembly constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 08/34] target/mips: Define R5900 MMI2 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 09/34] target/mips: Define R5900 MMI3 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 05/34] target/mips: Define R5900 MMI{0, 1, 2, 3} subclasses and MMI opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 07/34] target/mips: Define R5900 MMI1 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 11/34] target/mips: Placeholder for R5900 LQ,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 04/34] target/mips: Define R5900 MMI class, and LQ and SQ opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 06/34] target/mips: Define R5900 MMI0 opcode constants, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 03/34] target/mips: R5900 Multimedia Instruction overview note, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 23/34] tests/tcg/mips: Test R5900 three-operand MULT, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 12/34] target/mips: Placeholder for R5900 MMI instruction class, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 18/34] target/mips: Support R5900 three-operand MULT1 and MULTU1 instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 17/34] target/mips: Support R5900 three-operand MULT and MULTU instructions, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 28/34] tests/tcg/mips: Test R5900 MTLO1 and MTHI1, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 22/34] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Aleksandar Markovic, 2018/10/22
- [Qemu-devel] [PULL 20/34] target/mips: Support R5900 DIV1 and DIVU1 instructions, Aleksandar Markovic, 2018/10/22