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[Qemu-devel] [PATCH v8 34/38] tests/tcg/mips: Test R5900 three-operand M
From: |
Fredrik Noring |
Subject: |
[Qemu-devel] [PATCH v8 34/38] tests/tcg/mips: Test R5900 three-operand MADD1 |
Date: |
Sun, 21 Oct 2018 17:43:22 +0200 |
User-agent: |
Mutt/1.10.1 (2018-07-13) |
Signed-off-by: Fredrik Noring <address@hidden>
---
tests/tcg/mips/mipsr5900/madd.c | 43 +++++++++++++++++++++++++++++----
1 file changed, 38 insertions(+), 5 deletions(-)
diff --git a/tests/tcg/mips/mipsr5900/madd.c b/tests/tcg/mips/mipsr5900/madd.c
index 9ad2ea6dbb..f6f215e1c3 100644
--- a/tests/tcg/mips/mipsr5900/madd.c
+++ b/tests/tcg/mips/mipsr5900/madd.c
@@ -1,5 +1,5 @@
/*
- * Test R5900-specific three-operand MADD.
+ * Test R5900-specific three-operand MADD and MADD1.
*/
#include <stdio.h>
@@ -29,12 +29,45 @@ int64_t madd(int64_t a, int32_t rs, int32_t rt)
return r;
}
+int64_t madd1(int64_t a, int32_t rs, int32_t rt)
+{
+ int32_t lo = a;
+ int32_t hi = a >> 32;
+ int32_t rd;
+ int64_t r;
+
+ __asm__ __volatile__ (
+ " mtlo1 %5\n"
+ " mthi1 %6\n"
+ " madd1 %0, %3, %4\n"
+ " mflo1 %1\n"
+ " mfhi1 %2\n"
+ : "=r" (rd), "=r" (lo), "=r" (hi)
+ : "r" (rs), "r" (rt), "r" (lo), "r" (hi));
+ r = ((int64_t)hi << 32) | (uint32_t)lo;
+
+ assert(a + (int64_t)rs * rt == r);
+ assert(rd == lo);
+
+ return r;
+}
+
+static int64_t madd_variants(int64_t a, int32_t rs, int32_t rt)
+{
+ int64_t rd = madd(a, rs, rt);
+ int64_t rd1 = madd1(a, rs, rt);
+
+ assert(rd == rd1);
+
+ return rd;
+}
+
static void verify_madd(int64_t a, int32_t rs, int32_t rt, int64_t expected)
{
- assert(madd(a, rs, rt) == expected);
- assert(madd(a, -rs, rt) == a + a - expected);
- assert(madd(a, rs, -rt) == a + a - expected);
- assert(madd(a, -rs, -rt) == expected);
+ assert(madd_variants(a, rs, rt) == expected);
+ assert(madd_variants(a, -rs, rt) == a + a - expected);
+ assert(madd_variants(a, rs, -rt) == a + a - expected);
+ assert(madd_variants(a, -rs, -rt) == expected);
}
int main()
--
2.18.1
- [Qemu-devel] [PATCH v8 24/38] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, (continued)
- [Qemu-devel] [PATCH v8 24/38] target/mips: R5900 DMULT[U], DDIV[U], LL[D] and SC[D] are user only, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 25/38] tests/tcg/mips: Test R5900 three-operand MULT, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 27/38] tests/tcg/mips: Test R5900 three-operand MULT1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 26/38] tests/tcg/mips: Test R5900 three-operand MULTU, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 28/38] tests/tcg/mips: Test R5900 three-operand MULTU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 29/38] tests/tcg/mips: Test R5900 MFLO1 and MFHI1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 30/38] tests/tcg/mips: Test R5900 MTLO1 and MTHI1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 31/38] tests/tcg/mips: Test R5900 DIV1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 32/38] tests/tcg/mips: Test R5900 DIVU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 33/38] tests/tcg/mips: Test R5900 three-operand MADD, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 34/38] tests/tcg/mips: Test R5900 three-operand MADD1,
Fredrik Noring <=
- [Qemu-devel] [PATCH v8 35/38] tests/tcg/mips: Test R5900 three-operand MADDU, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 36/38] tests/tcg/mips: Test R5900 three-operand MADDU1, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 37/38] target/mips: Define the R5900 CPU, Fredrik Noring, 2018/10/21
- [Qemu-devel] [PATCH v8 38/38] linux-user/mips: Recognise the R5900 CPU model, Fredrik Noring, 2018/10/21
- Re: [Qemu-devel] [PATCH v8 00/38] target/mips: Limited support for the R5900, Aleksandar Markovic, 2018/10/22