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[Qemu-devel] [PATCH v5 11/14] target/mips: Add emulation of MXU instruct
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PATCH v5 11/14] target/mips: Add emulation of MXU instruction D16MUL |
Date: |
Fri, 19 Oct 2018 18:33:45 +0200 |
From: Craig Janeczek <address@hidden>
Add support for emulating the D16MUL MXU instruction.
Signed-off-by: Craig Janeczek <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 66 ++++++++++++++++++++++++++++++++++++++++++++++---
1 file changed, 63 insertions(+), 3 deletions(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 71a6533..ea7fe0c 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -23496,6 +23496,68 @@ static void gen_mxu_s8ldd(DisasContext *ctx)
tcg_temp_free(t1);
}
+/*
+ * D16MUL XRa, XRb, XRc, XRd, optn2 - Signed 16 bit pattern multiplication
+ */
+static void gen_mxu_d16mul(DisasContext *ctx)
+{
+ TCGv t0, t1, t2, t3;
+ TCGLabel *l0;
+ uint32_t XRa, XRb, XRc, XRd, optn2;
+
+ t0 = tcg_temp_new();
+ t1 = tcg_temp_new();
+ t2 = tcg_temp_new();
+ t3 = tcg_temp_new();
+
+ l0 = gen_new_label();
+
+ XRa = extract32(ctx->opcode, 6, 4);
+ XRb = extract32(ctx->opcode, 10, 4);
+ XRc = extract32(ctx->opcode, 14, 4);
+ XRd = extract32(ctx->opcode, 18, 4);
+ optn2 = extract32(ctx->opcode, 22, 2);
+
+ gen_load_mxu_cr(t0);
+ tcg_gen_andi_tl(t0, t0, MXU_CR_MXU_EN);
+ tcg_gen_brcondi_tl(TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
+
+ gen_load_mxu_gpr(t1, XRb);
+ tcg_gen_sextract_tl(t0, t1, 0, 16);
+ tcg_gen_sextract_tl(t1, t1, 16, 16);
+ gen_load_mxu_gpr(t3, XRc);
+ tcg_gen_sextract_tl(t2, t3, 0, 16);
+ tcg_gen_sextract_tl(t3, t3, 16, 16);
+
+ switch (optn2) {
+ case MXU_OPTN2_WW: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */
+ tcg_gen_mul_tl(t3, t1, t3);
+ tcg_gen_mul_tl(t2, t0, t2);
+ break;
+ case MXU_OPTN2_LW: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */
+ tcg_gen_mul_tl(t3, t0, t3);
+ tcg_gen_mul_tl(t2, t0, t2);
+ break;
+ case MXU_OPTN2_HW: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */
+ tcg_gen_mul_tl(t3, t1, t3);
+ tcg_gen_mul_tl(t2, t1, t2);
+ break;
+ case MXU_OPTN2_XW: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */
+ tcg_gen_mul_tl(t3, t0, t3);
+ tcg_gen_mul_tl(t2, t1, t2);
+ break;
+ }
+ gen_store_mxu_gpr(t3, XRa);
+ gen_store_mxu_gpr(t2, XRd);
+
+ gen_set_label(l0);
+
+ tcg_temp_free(t0);
+ tcg_temp_free(t1);
+ tcg_temp_free(t2);
+ tcg_temp_free(t3);
+}
+
/*
* Decoding engine for MXU
@@ -24476,9 +24538,7 @@ static void decode_opc_mxu(CPUMIPSState *env,
DisasContext *ctx)
decode_opc_mxu__pool02(env, ctx);
break;
case OPC_MXU_D16MUL:
- /* TODO: Implement emulation of D16MUL instruction. */
- MIPS_INVAL("OPC_MXU_D16MUL");
- generate_exception_end(ctx, EXCP_RI);
+ gen_mxu_d16mul(ctx);
break;
case OPC_MXU__POOL03:
decode_opc_mxu__pool03(env, ctx);
--
2.7.4
- [Qemu-devel] [PATCH v5 03/14] target/mips: Add and integrate MXU decoding engine placeholder, (continued)
- [Qemu-devel] [PATCH v5 03/14] target/mips: Add and integrate MXU decoding engine placeholder, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 04/14] target/mips: Add MXU decoding engine, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 05/14] target/mips: Add bit encoding for MXU add/subtract patterns 'aptn2', Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 08/14] target/mips: Add emulation of non-MXU MULL within MXU decoding engine, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 14/14] target/mips: Add emulation of MXU instructions S32LDD and S32LDDR, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 07/14] target/mips: Add bit encoding for MXU operand getting patterns 'optn3', Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 06/14] target/mips: Add bit encoding for MXU operand getting patterns 'optn2', Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 10/14] target/mips: Add emulation of MXU instruction S8LDD, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 11/14] target/mips: Add emulation of MXU instruction D16MUL,
Aleksandar Markovic <=
- [Qemu-devel] [PATCH v5 09/14] target/mips: Add emulation of MXU instructions S32I2M and S32M2I, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 12/14] target/mips: Add emulation of MXU instruction D16MAC, Aleksandar Markovic, 2018/10/19
- [Qemu-devel] [PATCH v5 13/14] target/mips: Add emulation of MXU instructions Q8MUL and Q8MULSU, Aleksandar Markovic, 2018/10/19