Re: [Qemu-devel] [PATCH v2 3/3] target/arm: Flush only the TLBs affected by TTBR*_EL1

[Richard Henderson]

On 10/19/18 9:12 AM, Peter Maydell wrote:
> A conservative check is probably:
>   if arm_current_el() < 3
>      // TTBR definitely can only be affecting the EL0/1
>      // translation regime for the current security state
>      if arm_is_secure_below_el3()
>         if EL3 is AArch32
>             flush S1SE0, S1E3
>         else
>             flush S1SE0, S1SE1
>      else
>         flush S12NSE1, S12NSE0
>   else
>      // err on the side of flushing more than maybe we need to
>      flush S1SE0, S12NSE1, S12NSE0
>      if EL3 is AArch32
>           flush S1E3
>      else
>           flush S1SE1
> 
> (but you should check my logic ;-))

Riiight.

Clearly it would be simpler and safer to track unused tlbs within cputlb.c.

> We do for AArch32 with TTBCR.EAE == 1 (ie LPAE, when you want to
> use the 64-bit form of the register, accessed via MRRC/MCRR).
> cpreg_field_is_64bit() is true for both "AArch64 sysreg" and
> "AArch32 64-bit cp reg".

Ok, thanks.

So drop this patch for now and I'll get back to it.  The other two in this
series are at least incremental improvement in the meantime.


r~