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[Qemu-devel] [PULL 09/27] target/mips: Add basic description of MXU ASE
From: |
Aleksandar Markovic |
Subject: |
[Qemu-devel] [PULL 09/27] target/mips: Add basic description of MXU ASE |
Date: |
Wed, 17 Oct 2018 14:33:37 +0200 |
From: Aleksandar Markovic <address@hidden>
Add a comment that contains a basic description of MXU ASE.
Reviewed-by: Stefan Markovic <address@hidden>
Signed-off-by: Aleksandar Markovic <address@hidden>
---
target/mips/translate.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index ab16cdb..46655bb 100644
--- a/target/mips/translate.c
+++ b/target/mips/translate.c
@@ -1389,6 +1389,26 @@ enum {
OPC_BINSRI_df = (0x7 << 23) | OPC_MSA_BIT_09,
};
+
+/*
+ * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET
+ * ============================================
+ *
+ * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of MIPS32
+ * instructions set. It is designed to fit the needs of signal, graphical and
+ * video processing applications. MXU instruction set is used in Xburst family
+ * of microprocessors by Ingenic.
+ *
+ * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is
+ * the control register.
+ *
+ * Compiled after:
+ *
+ * "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit
+ * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017
+ */
+
+
/* global register indices */
static TCGv cpu_gpr[32], cpu_PC;
static TCGv cpu_HI[MIPS_DSP_ACC], cpu_LO[MIPS_DSP_ACC];
--
2.7.4
- [Qemu-devel] [PULL 00/27]MIPS pull request for October 2018 - part 1, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 05/27] linux-user: Add MIPS-specific prctl() options, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 04/27] elf: Add Mips_elf_abiflags_v0 structure, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 09/27] target/mips: Add basic description of MXU ASE,
Aleksandar Markovic <=
- [Qemu-devel] [PULL 10/27] target/mips: Add assembler mnemonics list for MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 01/27] mailmap: Add an item for Yongbok Kim, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 07/27] target/mips: Add a comment with an overview of CP0 registers, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 14/27] target/mips: Reorganize bit definitions for insn_flags (ISAs/ASEs flags), Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 08/27] target/mips: Add a comment before each CP0 register section in cpu.h, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 13/27] target/mips: Increase 'supported ISAs/ASEs' flag holder size, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 06/27] linux-user: Add infrastructure for handling MIPS-specific prctl(), Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 11/27] target/mips: Add organizational chart of MXU ASE, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 25/27] target/mips: Fix emulation of microMIPS R6 <SELEQZ|SELNEZ>.<D|S>, Aleksandar Markovic, 2018/10/17
- [Qemu-devel] [PULL 27/27] target/mips: Add opcodes for nanoMIPS EVA instructions, Aleksandar Markovic, 2018/10/17